VHDL Implementation of UART with Status

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Project Seminar
on
By
Huma Nishad
Farzana Naushun
Shagufta Iram
Vrushali AH
7
th
Sem ECE PDA College Gulbarga
IN FEW Mints.
1. Abstract
2. Literature survey
3. Problem Definition
4. Objective
5. Design Approach
6. Requirement
7. Conclusion
Reference
1. Abstract
In parallel communication the cost as well as complexity of the
system increases due to simultaneous transmission of data bits on
multiple wires.
Serial communication alleviates this drawback and emerges as
effective candidate in many applications for long distance
communication as it reduces the signal distortion because of its
simple structure.
This paper focuses on the VHDL implementation of UART with status
register which supports asynchronous serial communication.
The paper presents the architecture of UART which indicates,
during reception of data, Parity Error, Framing Error, Overrun
Error And Break Error Using Status Register.
2. Literature Survey
1. A NEW APPROACH TO REALIZE UART
Yongcheng Wang ; Changchun Inst. of Opt., Chinese Acad. of Sci.,
Changchun, China ; Kefei Song
In this paper its describes about the simple implementation of UART

2. DESIGN AND SIMULATION OF UART SERIAL COMMUNICATION MODULE
BASED ON VHDL
Fang Yi-yuan ; Coll. of Electr. & Electron. Eng., Shanghai Univ. of Eng. Sci.,
Shanghai, China ; Chen Xue-jun

3. OPTIMIZATION OF UART COMMUNICATION BASED ON LEON2
HARDWARE DEBUG SUPPORT UNIT
Mintao Liu ; Dept. of Electron. Eng, Xiamen Univ., Xiamen ; Jianyang Zhou

2. Literature Survey
4. Research of Automatic Digital Multi meter Interface Technology
Based on UART
Jing, Huang ; Leling, Qiao ; Hanbo, Zhang

5. Optimal implementation of UART-SPI interface in soc
This paper details the design and implementation of SoC's UART-SPI
Interface. The UART-SPI interface provides usage for the universal
asynchronous receiver/transmitter (UART) to serial peripheral interface
(SPI). This interface can be used to communicate to SPI slave devices
from a PC with UART port. The interface consists of three blocks:
the UART interface, the UART-to-SPI interfacing block and the SPI
Master interface.



3. Problem Definition
Various designs are found in literatures for UART as different
systems have different requirements and attributes which require
data communication between its functional units.
In recent years the researchers have proposed various UART
designs like automatic baud rate synchronizing capability[,
predictable timing behavior to allow the integration of nodes with
imprecise clocks in time-triggered real-time systems, recursive
running sum filter to remove noisy samples, integration of only
core functions into a FPGA chip to achieve compact, stable and
reliable data transmission to avoid waste of resources and
decrease cost, programmable logic to enable interfacing
between asynchronous communications protocols and DSP having
synchronous serial ports.
4. Objective
The goal is to design, implement UART with Status Register which
includes following Three Modules.
Baud Rate Generator,
Receiver And
Transmitter.
The proposed design of UART satisfies the system requirements of
high integration, stabilization, low bit error rate, and low cost.
It also supports configurable baud rate generator and variable data
length from 5-8 bits per frame.
5. Design Approach
Transmitter
Baud Rate
Generator
Receiver
Txin 8 bit
Rxin 8 bit
WR
RD
Tx Out 8 bit
4- Error
Bit
6. Requirement Analysis
ModelSim for Simulation.
Quartrus II 10.1 for FPGA Implementation.
VHDL Coding
8. Conclusion
REFERENCES
1. Elmenreich, W.; Delvai, M.; , "Time-triggered communication with
UARTs," Factory Communication Systems, 2002. 4th IEEE
International Workshop on , vol., no., pp. 97- 104, 2002J. Clerk
Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. Oxford:
Clarendon, 1892, pp.6873.
2. Gallo, R.; Delvai, M.; Elmenreich, W.; Steininger, A.; , "Revision and
verification of an enhanced UART," Factory Communication Systems,
2004. Proceedings. 2004 IEEE International Workshop on , vol., no.,
pp. 315- 318, 22-24 Sept. 2004..
3. Norhuzaimin, J.; Maimun, H.H.; , "The design of high speed UART,
Applied Electromagnetics, 2005. APACE 2005. Asia-Pacifi Conference on
, vol., no., pp.5 pp., 20-21 Dec. 2005.
4. Himanshu Patel; Sanjay Trivedi; R. Neelkanthan; V. R. Gujraty; , "A
Robust UART Architecture Based on Recursive Running Sum Filter for
Better Noise Performance," VLSI Design, 2007.
UART RS-232
RS-232 Pin Assignment
FPGA over-all Test
receiver
transmitter
start
debounce
data=[a]= 0x61
tx
rx
Data_ready
data
PC
PC
(1) When buttons is pushed , PC receive : [a]= 0x61
(2) PC send data to FPGA : data are displayed on leds
=> Use HyperTerminal to send and receive data