PROJECT PRESENTATION

ROHIT KASHYAP

ABHISHEK SINGH

VIRENDRA KUMAR

MEENAKSHI TRIPATHI
The controller to be designed
controls the traffic lights of a
busy highway (HWY)
intersecting,
a side road (SRD) that has
relatively lighter traffic load.
Sensors at the intersection
detect the presence of cars on
the highway and side road.

Forty to fifty years ago when
traffic volume was lighter, the
main job of traffic light systems
was to manage peak traffic
during the day .
The lights were centrally
controlled, and not
programmed to adjust in real
time.
They were mostly optimized for
pre-established assumed
situations.
Our aim is to design an error free traffic control system that
Safely,
effectively directs traffic for streets intersection.
The concern is
minimization of traffic congestion,
better regulation of traffic and minimization of travel time.
Advantages are reduction in vehicle operating cost,
more efficient use of engines ,
lower environmental pollution from vehicle emissions,
safe regulation of traffic in rush hour as well as in normal
daily traffic.
The system should have complete reliability confirming the
timing of lights which must not cause accidents and safe
crossing of pedestrians.
Major design issues of traffic control system include traffic
bottlenecks, priority of pedestrian crossing, and easy
implementation of changes along with reliable and
sustainable design
Xilinx tools : -
1. Project navigator.
2. Modelsim simulator

Hardware used
FPGA kit
VHDL :VHSIC [Very High Speed Integrated Circuits]
hardware description language.

VHDL was developed as an alternative to huge, complex
manuals which were subject to implementation-specific details.
VHDL supports description of components as well as
systems at various levels of abstraction- Gate and
component delays, Clock cycles, Abstract behavior
A basic VHDL code has following structural
components:
1. Libraries e.g :IEEE.STD_LOGIC_1164.ALL
2. Entity contains I/P and O/P declaration bits
3. Architecture contains all logic.







Interface
(entity Declaration)
BODY
(Architecture)
Sequential
combinational
Process
Subprograms
Ports
VHDL Entity
VHDL Examples: AND
Gate
entity AND2 is
port (a, b: in
bit ;
c : out bit);
end AND2;

architecture beh
of AND2 is
begin
c <= a and
b;
end beh;

AND GATE
a
b
c
S<=A+B
Behavioral
Dataflow
Structural
(components
interconnections)
Levels of abstraction: Behavioral, Structural and Physical
Physical
Implementation
VHDL is a parallel language while C is procedural
language. Each statement occurring in VHDL is executed
concurrently i.e. all statements run simultaneously .
In C/C++each statement is executed in sequential order and
its own turn., In VHDL explicit constructs exist for sequential
steps.

VHDL allows use of explicit time delay, which is not
applicable in procedural language.
VHDL model cannot be implemented in real time application
directly like other procedural languages. It is simulated and
synthesized using in built in system clock.



Logic optimization
Technology mapping
Placement
Routing
Programming Unit
Configured FPGA (Field-Programmable Gate arrays)
Initial design entry
Design flow of an Integrated circuit
A field-programmable gate array (FPGA) is a
semiconductor device that can be configured by the customer
or designer after manufacturinghence the name "field-
programmable".
FPGAs are programmed using a logic circuit diagram or a
source code in a hardware description language (HDL) to
specify how the chip will work.
They can be used to implement any logical function that an
application-specific integrated circuit (ASIC) could perform,
but the ability to update the functionality after shipping
offers advantages for many applications.
Clock process is edge triggered ,therefore states
change for every transition of 0 to 1 .
Reset the process initiates for binary value 1,
further the value is set to low.
Sensor - the value 1 signifies more traffic load, hence
duration of green light increases .




The states depend upon the following port values :
Smooth sea never made a skilled mariner
Hence the constant cross checking of knowledge and
guidance is provided by Mr. P.K. Bharti (H.O.D.
Computer science) and Mr. Amit Goswami
(mentor), Mr.Virendra kumar.

ROHIT KASHYAP
MEENAKSHI TRIPATHI
ABHISHEK SINGH
VIRENDRA KUMAR