Introduction to CMOS

VLSI Design
Instructed by Shmuel Wimer
Bar-Ilan University, Engineering Faculty
Technion, EE Faculty

Credits: David Harris
Harvey Mudd College

(Some materials copied/taken/adapted from
Harris lecture notes)
CMOS VLSI Design
2
Oct 2010
Course Topics

Introduction to CMOS circuits
MOS transistor theory, processing technology
CMOS circuit and logic design
System design methods
CAD algorithms for backend design
Case studies, CAD tools, etc.

CMOS VLSI Design
3
Oct 2010
Bibliography
Textbook
Weste and Harris.
CMOS VLSI Design
(3
rd
edition)
Addison Wesley
ISBN: 0-321-14901-7
Available at
amazon.com.

CMOS VLSI Design
4
Oct 2010
Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Introduction: How to build your own simple CMOS
chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
CMOS VLSI Design
5
Oct 2010
A Brief History
1958: First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2003
Intel Pentium 4 mprocessor (55 million transistors)
512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
CMOS VLSI Design
6
Oct 2010
Annual Sales
10
18
transistors manufactured in 2003
100 million for every human on the planet
0
50
100
150
200
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year
G
l
o
b
a
l

S
e
m
i
c
o
n
d
u
c
t
o
r

B
i
l
l
i
n
g
s
(
B
i
l
l
i
o
n
s

o
f

U
S
$
)
CMOS VLSI Design
7
Oct 2010
Invention of the Transistor
Vacuum tubes ruled in first half of 20
th
century
Large, expensive, power-hungry, unreliable
1947: first point contact transistor
John Bardeen and Walter Brattain at Bell Labs
Read Crystal Fire
by Riordan, Hoddeson
CMOS VLSI Design
8
Oct 2010
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls
large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current
between source and drain
Low power allows very high integration
CMOS VLSI Design
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Oct 2010
1970s processes usually had only nMOS transistors
Inexpensive, but consume power while idle







1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit mProc
CMOS VLSI Design
10
Oct 2010
Moores Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Year
T
r
a
n
s
i
s
t
o
r
s
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro
Pentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
CMOS VLSI Design
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Oct 2010
CMOS VLSI Design
12
Oct 2010
CMOS VLSI Design
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Oct 2010
CMOS VLSI Design
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Oct 2010
Corollaries
Many other factors grow exponentially
Ex: clock frequency, processor performance
Year
1
10
100
1,000
10,000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro/II/III
Pentium 4
C
l
o
c
k

S
p
e
e
d

(
M
H
z
)
CMOS VLSI Design
15
Oct 2010
Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Si Si Si
Si Si Si
Si Si Si
CMOS VLSI Design
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Oct 2010
Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
As Si Si
Si Si Si
Si Si Si
B Si Si
Si Si Si
Si Si Si
-
+
+
-
CMOS VLSI Design
17
Oct 2010
p-n Junctions
A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction

p-type n-type
anode
cathode
CMOS VLSI Design
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Oct 2010
nMOS Transistor
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO
2
(oxide) is a very good insulator
Called metal oxide semiconductor (MOS)
capacitor
Even though gate is
no longer made of metal
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
CMOS VLSI Design
19
Oct 2010
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
0
S
CMOS VLSI Design
20
Oct 2010
nMOS Operation Cont.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
1
S
CMOS VLSI Design
21
Oct 2010
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (V
DD
)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
CMOS VLSI Design
22
Oct 2010
Power Supply Voltage
GND = 0 V
In 1980s, V
DD
= 5V
V
DD
has decreased in modern processes
High V
DD
would damage modern tiny transistors
Lower V
DD
saves power
V
DD
= 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
CMOS VLSI Design
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Oct 2010
Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
CMOS VLSI Design
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Oct 2010
CMOS Inverter
A Y
0
1
V
DD
A Y
GND
A Y
CMOS VLSI Design
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Oct 2010
CMOS Inverter
A Y
0
1 0
V
DD
A=1 Y=0
GND
ON
OFF
A Y
CMOS VLSI Design
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Oct 2010
CMOS Inverter
A Y
0 1
1 0
V
DD
A=0 Y=1
GND
OFF
ON
A Y
CMOS VLSI Design
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Oct 2010
CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
A
B
Y
CMOS VLSI Design
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Oct 2010
CMOS NAND Gate
A B Y
0 0 1
0 1
1 0
1 1
A=0
B=0
Y=1
OFF
ON
ON
OFF
CMOS VLSI Design
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Oct 2010
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0
1 1
A=0
B=1
Y=1
OFF
OFF
ON
ON
CMOS VLSI Design
30
Oct 2010
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1
A=1
B=0
Y=1
ON
ON
OFF
OFF
CMOS VLSI Design
31
Oct 2010
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A=1
B=1
Y=0
ON
OFF
OFF
ON
CMOS VLSI Design
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Oct 2010
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
B
Y
CMOS VLSI Design
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Oct 2010
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
A
B
Y
C
CMOS VLSI Design
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Oct 2010
Compound Gates
Compound gates can do any inverting function
Ex: (AND-AND-OR-INVERT, AOI22) Y A B C D
A
B
C
D
A
B
C
D
A B C D
A B
C D
B
D
Y
A
C
A
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
CMOS VLSI Design
35
Oct 2010
Example: O3AI


Y A B C D
A B
Y
C
D
D C
B
A
CMOS VLSI Design
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Oct 2010
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process
CMOS VLSI Design
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Oct 2010
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
CMOS VLSI Design
38
Oct 2010
Well and Substrate Taps
Substrate must be tied to GND and n-well to V
DD
Metal to lightly-doped semiconductor forms poor
connection (used for Schottky Diode)
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
substrate tap well tap
n+ p+
CMOS VLSI Design
39
Oct 2010
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND V
DD
Y
A
substrate tap
well tap
nMOS transistor pMOS transistor
CMOS VLSI Design
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Oct 2010
CMOS VLSI Design
41
Oct 2010
Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
CMOS VLSI Design
42
Oct 2010
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO
2
(oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO
2
p substrate
CMOS VLSI Design
43
Oct 2010
Oxidation
Grow SiO
2
on top of Si wafer
900 1200 C with H
2
O or O
2
in oxidation furnace
p substrate
SiO
2
CMOS VLSI Design
44
Oct 2010
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
p substrate
SiO
2
Photoresist
CMOS VLSI Design
45
Oct 2010
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
p substrate
SiO
2
Photoresist
CMOS VLSI Design
46
Oct 2010
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
p substrate
SiO
2
Photoresist
CMOS VLSI Design
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Oct 2010
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranha etch
Necessary so resist doesnt melt in next step
p substrate
SiO
2
CMOS VLSI Design
48
Oct 2010
n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO
2
, only enter exposed Si
n well
SiO
2
CMOS VLSI Design
49
Oct 2010
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
p substrate
n well
CMOS VLSI Design
50
Oct 2010
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH
4
)
Forms many small crystals called polysilicon
Heavily doped to be good conductor

Thin gate oxide
Polysilicon
p substrate
n well
CMOS VLSI Design
51
Oct 2010
Polysilicon Patterning
Use same lithography process to pattern polysilicon

Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
CMOS VLSI Design
52
Oct 2010
N-diffusion
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact

p substrate
n well
CMOS VLSI Design
53
Oct 2010
N-diffusion (cont.)
Pattern oxide and form n+ regions
p substrate
n well
n+ Diffusion
CMOS VLSI Design
54
Oct 2010
N-diffusion (cont.)
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion

n well
p substrate
n+ n+ n+
CMOS VLSI Design
55
Oct 2010
N-diffusion (cont.)
Strip off oxide to complete patterning step
n well
p substrate
n+ n+ n+
CMOS VLSI Design
56
Oct 2010
P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p substrate
n well
n+ n+ n+ p+ p+ p+
CMOS VLSI Design
57
Oct 2010
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
Contact
CMOS VLSI Design
58
Oct 2010
Metalization
Sputter on copper / aluminum over whole wafer
Pattern to remove excess metal, leaving wires

p substrate
Metal
Thick field
oxide
n well
n+ n+ n+ p+ p+ p+
Metal
CMOS VLSI Design
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Oct 2010
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size scales ~X0.7 every 2 years both lateral
and vertical
Moores law
Normalize feature size when describing design rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
Todays l = 0.01 mm (10 nanometer = 10
-8
meter)
CMOS VLSI Design
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Oct 2010
Simplified Design Rules
Conservative rules to get you started
CMOS VLSI Design
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Oct 2010
Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4l / 2l, sometimes called 1 unit
In f = 0.01 mm process, this is 0.04 mm wide, 0.02
mm long
CMOS VLSI Design
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Oct 2010
Summary
MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start
designing schematics and layout for a simple circuit!