PIPELINING

ENS 5257:

MICROPROCESSOR SYSTEMS
PRESENTATION BY
SAJID HAYAT

What Is Pipelining?
Pipelining is almost used by all of the

microprocessors now a days.

It enhances the performance of the system in terms
of throughput by overlapping the instructions.
A common example of a pipeline is a factory making
cars. Assume there are three stages of making the
car:
1.
2.
3.

Engine
Body
Painting

For simplicity, we assume that each stage takes 1

hour.

If only one team of workers is working on the car,

it would take three hours for one car to be

completed.
If we have three teams, 1st team can work on
engine
Upon completing stage 1, they can pass it on to
2nd team who can work on the body of the car.
On the same time as the body of the car is being
constructed, the first team is working on the
engine of the next car
As each stage takes 1 hour there is no waiting, so
we can produce one car per hour

3hrs

Engin
e

Body

3hrs

3hrs

Paint
Engin
e

Body

Paint
Engin
e

Figure 1: Example of unpipelined construction of cars

Body

Paint

1hr

1hr

1hr

Engin
e

Body

Paint

Engin
e

Body

Paint

Engin
e

Body

1hr

1hr

Paint

Figure 2: Example of pipelined construction of cars

Pipelining characteristics
In CPU, the concept of pipelining is such that

the instruction is broken up into various

stages.
All the stages start simultaneously
If all the stages are balanced the time taken
by each instruction is defined by:
Time taken per

instruction
instruction

Time per un-pipelined

pipelined

Number of stages

Pipelining Characteristics
Pipelining reduces the average instruction

time which therefore reduces average cycles

per instruction CPI

Latency

It is the time required by an instruction to

propagate through the pipeline

Throughput

It is defined as the rate of starting and

finishing of instructions

Implementation of RISC Instruction Set

without pipelining
At first we will see how RISC instruction set is

implemented without pipelining. We assume

that each instruction can be executed in 5 clock
cycles.
These 5 clock cycles can be broken up as
follows:
Instruction

Fetch Cycle
Instruction Decode / Register Fetch Cycle
Execution Cycle
Memory Access Cycle
Write Back Cycle

Instruction Fetch Cycle

The value of PC represents a memory address
The data of that memory address is loaded

into CPU
The PC is then incremented which represents
the memory address of next instruction

Instruction Decode (ID)/Register Fetch Cycle

In this cycle the instruction is decoded while at the

same time the values of the registers involved is read.

Execution Cycle

In this cycle the Arithmetic Logic Unit

executes the instruction which can be a

memory reference, Register - register or
Register immediate.

Memory Access Cycle

In this cycle the data transfer takes place which

can be either read or write (to the address

calculated in the previous cycle, if so).

Write-Back Cycle
In Register Register instruction, the resulting

data is written to the related register.

Pipelining of 5 Stage RISC instruction set

In ideal pipelining implementation at every

clock cycle a new instruction is started.

In reality this cannot be achieved because the
ALU cannot do a Multiplication and Addition
operation at the same time
But if instruction execution stages are
independent, we can see how they are
overlapped

Pipelining Example
Assuming a 5 stage pipeline in which each

stage take the time 10ns, 8ns, 10ns, 9ns, 7ns

respectively.
For un-pipelined
Avg time taken per instruction =
10+8+10+9+7 = 44ns
For pipelined
Lets consider each stage has an over head of
1ns while slowest stage takes 10ns so it sums
up to 11ns
Speedup = un-pipelined time/pipelined time

Figure 3: Implementation of instruction set with 5 stage pipelining

Pipelining Hazards
The hazards prevent the next instruction in an

instruction stream to be executed in its

allocated clock cycle. They can be of three
categories
Structural Hazards
Data Hazards
Control Hazards

Structural Hazards
They occur due to resource conflicts when

hardware is unable to support overlapped

execution of instructions

Data Hazards

They occur if an instruction is depending on the result

from the instruction overlapped in the pipeline.

Control Hazards
The control hazard occurs if an instruction

changes the value of PC.

Eliminating the Pipeline

Hazard
The pipeline hazard makes it necessary to

stall the pipeline

To eliminate the pipeline hazard some
instructions are allowed to proceed while
some are delayed.
The instructions issued before the stall are
allowed to be executed.

Conclusion
Pipelining increases the efficiency of the

processor considerably
The Pipeline Hazards must be addressed
properly
The performance gained by pipelining
depends on avoiding the Pipeline stalls
because they degrade the overall throughput

References
1.
2.
3.
4.
5.

http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/hazar
ds.html
http://arstechnica.com/features/2004/09/pipelining-2/
http://www.psut.edu.jo/sites/qaralleh/CO/co_doc/chapte
r%208%20-%20%20Pipelining.ppt
www.engr.mun.ca/~venky/Pipelining
http://www.techrepublic.com/article/solutionbase-how-pipe
lining-and-multiple-cores-help-speed-cpus/

Thank
you