Device Modeling for RFIC Design/Simulation

T.H.Huang
Chapter 10

Analog Design Pitfalls
Part-I: Matching Issue of Capacitor/Resistor Layout;
Part-II: Analog Design Pitfalls
Why Matching is important in analog?
Basic operation requirement on device matching:
> pipelined A/D converters;

Common mode rejection limited by matching:
> OP Amp;

Supply noise rejection limited by mismatch in
fully-differential circuit.

Amplifier offsets degrades the performance:
> Bandgap reference
Part I. Matching Issues
Pipelined A/D Converter Architecture:
Sample
/Hold
Stage 1 Stage 2 Stage M
Digital Correction : p+q++r bits
Analog
input
p-bits q-bits r-bits
Digital
output
Sample
/Hold
+
Gain
P-bit
ADC
P-bit
DAC
residue
Stage N
(should be matched)
(p-bits)
Why Matching is important in Digital?
Timing / Skew;
In memories.
Unit-Matching Principle:
The general rule to make two components
electrically equivalent is simply to draw
them using identical unit-cells.

Two components are identical as if they
and their surroundings are identical.
A B
C
A B
C
Dummy pattern!
Common-Centroid Layout:
As you know the profile gradient on
the wafer Linear variation;
Matching Issue of Layout.
y= m x +b
O
x
i
d
e

T
h
i
c
k
n
e
s
s

O
r

D
o
p
i
n
g

C
o
n
c
e
n
t
r
a
t
i
o
n

Distance
y= m x + b
A)

B)
A1 A2 B
A1 B A2
y
x1 x2 x3
Common-Centroid Layout:
(1)For differential-circuits;
(2)Using unit identical cells;
(3)Example: if needs
(A1+A2) : B = 2 : 1
2;
b x2 m
2b x3) (x1 m
B
A2 A1
(B)
2;
b x3 m
2b x2) (x1 m
B
A2 A1
(A)
=
+
+ +
=
+
=
+
+ +
=
+
Common-Centroid Layout methodology: (for 4 Groups)
A C C B
D A B D
D B A D
B C C A
D B C A
C A D B
B D A C
A C B D
Methodology (I) Methodology (II)
Note: Balanced A, B, C, and D when linear gradient.
Symmetric Layout for Transistors:
(A) Interdigitized Layout;
(B) Common-centroid Layout.
(A):
Source: http://www.mosis.org/Technical/Layermaps/Im-scoms_scn3m.html
(B):
Note: Using (B), the drain parasitic capacitance
becomes different. unbalanced parasitics.
But could be better in current symmetry.
DC current mirror use!
Other Considerations:
Differential pair devices with the same direction;
Make use of dummy devices for better etching
uniformity.

(Not good!)
Capacitor (or resistor) Layout Issues:
-- Matching Concepts
(1) Unit matching principle: use of identical unit cells.

(2) Common-centroid layout; (if linear gradient problem exists)

(3) Using dummy cell around the edges;

(4) Minimize the ratio of the perimeter to the area
(a circle is optimum; N-sides shape is better)

(5) For parallel-plates capacitor, makes one plate is
larger than the other to eliminate alignment error.
Yiannoulos Path for Capacitance :
-- Keeping the same perimeter/area ratio.
Note:
Each unit cell
contributes
two sides
as the parasitics
source!
13 unit cells.
Resistor Layout Issues: *
* [source]: Andrea Baschirottos Lecture Note. http://microel.unipv.it/~andrea
Resistor Layout Issues: *
(if you know the
thermal gradient!)
Part II. Analog Design Pitfalls
IR drop Issue:
The Voltage drop in reference and Power
supply (Vcc) lines

affect
> voltage reference circuits;
> comparators.
Case 1: Grounded Line Drops:
1
2
g
1
2
bg o
1
bg
2
bg o
R
R
V
R
R
1 V V
R
Vg V
R
V V

|
|
.
|

\
|
+ =

10mA 100mV drop

Voltage divider
Remedies for case 1:
(1) Adding a pure Kelvin Line;
(2) Placing the bandgap, voltage divider, and
the OP Amp as closer to each other as possible.
Kelvin Path
Less drive current
flows in Kelvin path.
Case 2: Kelvin Line Resistance:
|
|
.
|

\
|
+ = =
|
|
.
|

\
|
+
+
+ =
1
2
bg o
1
2
g
p
g 1
p 2
bg ref
R
R
1 V V
R
R
R
R
if as
R R
R R
1 V V
Remedies for case 2:
(1) Increase feedback divider resistance to reduce
the significance of parasitic resistance;
(2) Locate the divider close to the reference voltage
and the grounded voltage.
30K
10K
It could affect
the BW, however.
Case 3: Reference Line Drop:
This reference
point could be
connected to
many nodes.
Remedies for case 3:
(1) Adding a pure Kelvin Line;
(2) Eleminating load currents from the reference line;
adding Buffer stage;
(3) Placing the bandgap, voltage divider, and
the OP Amp as closer to each other as possible.
To loads
IR drop on Power Supply Line:
Small voltage drops mirror current error!
For BJTs case current varies exponentially.
If the mirror path
too long!
5. ratio current mirror the (2)
line; power rough the current th drive tal greater to a (1)
case, general in And
2!
I
I
18mV, V When
V
V
exp
V
V V
exp
I
I
1 : 1 ratio size the if
V
V
exp I I
: BJT For
C2
C1
be
T
be
T
be2 be1
C2
C1
T
be
S C
>
= =
|
|
.
|

\
|
=
|
|
.
|

\
|

=
=
|
|
.
|

\
|
=
Remedies for mirror pairs:
(1) Mirror transistors are located as closer as possible;
(2) A wide and thick power line is used and to avoid of
using under-passes;
(3) Using like the figure below;
(4) Adding a certain-value emitter resistor to stablize
the collector current.

Shorten this path,
to provide a good
common node!
Emitter Resistance Feedback Effect:
+
+
|
C
be
C
I
makes in turn, This,
V
then
I As
Just means the
voltage disturbance
in simulation as shown next.
Simulation Results of Emitter Resistance Feedback:
M
i
r
r
o
r
e
d

C
o
l
l
e
c
t
o
r

C
u
r
r
e
n
t

For RF
application:
Noise
As R
e

Disturbance voltage
comes from the IR drop
of grounded lines.
Slope be
linearlized
by R
e
.
Parasitic PNP lateral bipolar effect:
(1)Current leakage from emitter to substrate;
(2)Low Beta in Large Area Lateral PNP.
Leakage Current Issue:
When a parasitic lateral PNP goes into saturation.
Current dumps from Emitter to Substrate via P2.
Experimental Results:
Negative collector current!
Current Gain (Beta) Drop Issue:
Recombination in buried region;
Emitter windows area/perimeter ratio ;
(Cont.)
Recombination:
Area Buttom
) (effective Perimeter
Beta Lateral
N-epi
N+ buried
Fermi level
Buried layer
Higher doping
Higher recombination
> Measurement Results:
10x10 um
2
26x26 um
2
NPN Bipolar Transistor Issues: Off leakage.
(Vertical) NPN BJT Features:

Electron High mobility;
Vertical profile High current gain;
Collector efficiency Higher driving capability.
Saturation NPN steals Base Current:
off
saturation
(parasitic pnp steals base
current)
I
3
becomes
abnormal
since base
current are
affected by
N4 saturation.
low
Transistor (N4) saturation effect
causes leakage from the parasitic pnp.
(cont.)
Remedy for N4 saturation case:
Add a high-resistance resistor in
series with the base of the possible
saturation transistors.
Temperature-Turn-ON-Transistor Effect:
Q2 plays as
a switch
to turn
off the
Q1.
Assumed Q2 ON,
To make Vce2
= 0.25V, only slightly
changed with T.
As T increases,
Q1 base current
increases, too.
It makes Io large
Malfunction of
V
out
.

Ex. @ Vbe=0.25V, IC=10nA @ 25C; IC=100uA @135C.
Illustration from SPICE model:
Desired
OFF
state.
Simulation Results of Is Temperature dependence:
Remedy for Temperature Turn ON Effect:
Make Q2 large enough to handle the leakage
current from Q1 at elevated temperature (high T).
To choose
Q2 large
enough.
Comparator Circuit Problems:
(1)Headroom failure : there is not enough voltage
across the transistor providing the bias current;

(2) The allowable range of input voltages is exceeded;

(3) Charge stored in a Darlington input causes an
erroneous comparison. (premature switching)
Three kinds of failure modes:
Case 1: Headroom Failure:
Operation:
Vin Low;
P2 OFF;
No current for G2;
I
2
L logic G3High;
Vout Low.
And
Vice versa.

I
2
L logic : G3
Malfunction:
As Vin from low
to high,
V
A
Vin+0.7
~ 2.8+0.7=3.5V,
Makes P3 fails
to provide current;
P2 off,
Vout no way
to change to High.
V
A
Vcc is not
high enough.
Case 1: Headroom Failure: another case
V
A
3.4V
As Vin High
Makes P3 off.
Malfunction:
Similar to the
Above case.
Vcc is not
high enough.
> Case 2 : Low input limit is exceeded
V
B
> 0.7V
to keep N1
N2 mirror pair
work.
V
B
Malfunction:
As Vin Low
bootstrap effect
makes V
B
below 0.7V,
OFF N1 and N2,
abnormal bias
N3.
High to low
Remedy for this case: add a Darlington input.
Replaced by
a Darlington pair.
V
B
Premature Switching Problem in a Delay circuit:
Operation:
Vin Low,
C1 charges
to turn off
P3 and P1,
makes Vout
low.
Malfunction:
P2s base parasitic
capacitance also
discharged by the
leakage of P4,
makes the charging
time longer.
Remedy for this case: add a Darlington input.
(1) Remedy #1:
Charged
by collector current.
Remedy for this case: add a Darlington input.
(1) Remedy #2:
By a compensation
current to fixed P2s
base voltage.
(concept of
pre-charge)
Latch up Issue: parasitic P-N-P-N path
Build up a low resistance path between
power rails;
Causing thermal destruction.
Mainly from the structure of CMOS.
PMOS
NMOS
Equivalent Model for Latch-up:
SCR:
Silicon
Controlled
Rectifier
4 possible
trigger points
Remedies for Latch-up:
Just reduce the probability to latch up;

(1) Placement of bias contacts between
PMOS and NMOS transistor decreases
the values of parasitic resistances;

(2) Reduce epi tub resistance (high doping
concentration, too) by contacting the
buried layer with a deep N diffusion;

(3) Using isolated MOS devices to increases
the base width of the parasitic lateral pnp,
to decrease its beta and loop gain of SCR.
(1) Reduce
Rs &
Rwell;

(2) Reduce
Beta &
Loop gain.
P-type-Resistor ISO EPI Latch-up Structure:
If use the diffusion resistor;
Parasitic PNPN path see the next figure;
Diffusion resistor
For RF application:
Avoid of use
of resistors!
Equivalent circuit:
Inductor helps
to trigger!
Thermal Destruction by Latch-up:
Remedy for this case:
The process
has to be able
to provide
Schottky
diode.
Shortage using the diffusion resistance:
Equivalent resistance
= 300 // Ro of PNP
(floating tub issue)
To provide
enough
voltage drop, too.
Resistors in Floating Tub:
Remedies for this case:
(1)Properly bias the tub;
(2) Increase the R1 and R2 spacing
to reduce the parasitic bipolar gain;
R1 R2
Parasitic Field-Oxide-MOS PNPN structure:
A parasitic structure in a multi-emitter device
as a metal line passing through.
Examples of Parasitic MOSFETs:

NPN transistor base and p-isolation;
NPN base and an underpass p-tub;
Underpass p-tub and p-isolation;
PNP collector to iso well;
PNP collector to p-resistors;
P-resistor to p-resistor.
OSFETs : channel formed by oxide charges

Examples:
PNP transistor emitter to collector;
PNP transistor collector to p-isolation;
NPN transistor base to p-isolation;
P-resistor to p-isolation;
P-resistor to p-resistor.
Remedy for OSFETs
Using n+ channel stop
Metal over Implanted Resistors Issues:

Shortage:
Rs variation.
For symmetric
consideration.
[the end]