VLSI Testing Class

Introduction to VLSI Testing

Kuen-Jong Lee

Dept. of Electrical Engineering
National Cheng-Kung University
Tainan, Taiwan
VLSI Testing NCKUEE-KJLEE
Introduction.2
Problems to Think
How are you going to test
A 32 bit adder
A 32 bit counter
A 32Mb cache memory
A 10
7
-transistor CPU
A 10
9
-transistor SOC
VLSI Testing NCKUEE-KJLEE
Introduction.3
OUTLINE
Introduction
Fault modeling
Fault simulation
Test generation
Automatic test pattern generation
(ATPG)
Design for testability
Built-in self test
Synthesis for testability
An example
VLSI Testing NCKUEE-KJLEE
Introduction.4
Basic Concept of Testing
Related fields
Verification: To verify the correctness of a
design
Diagnosis: To tell the faulty site
Reliability: To tell whether a good system will work
correctly or not after some time.
Debug: To find the faulty site and try to eliminate the fault
VDD
0/1
0
0
0
0
0
Testing: To tell whether a circuit is good or bad
VLSI Testing NCKUEE-KJLEE
Introduction.5
Why Studying Testing?
Economics!
Reduce test cost (enhance profit)
Automatic test equipment (ATE) is extremely
expensive
Shorten time-to-market
Market dominating or sharing
Guarantee IC quality and reliability
Defects detected in Cost
Wafer 0.01 0.1
Packaged chip 0.1 1
Board 1 10
System 10 100
Field 100 1000
Rule of Ten:
Cost to detect faulty
IC increases by an
order of magnitude

VLSI Testing NCKUEE-KJLEE
Introduction.6
Principle of Testing
Testing typically consists of
Applying set of test stimuli (input patterns, test vectors)
to inputs of circuit under test (CUT), and
Analyzing output responses
The quality of the tested circuits will depend upon
the thoroughness of the test vectors
Circuit
under
Test
(CUT)
-1011
11-00
-0-1-
01--0
0-101
1-001
0011-
-1101
1001-
01-11
Comparator
Stored
Correct
Response
Test Result
Input Patterns Output Response
VLSI Testing NCKUEE-KJLEE
Introduction.7
Importance of testing
N = # transistors in a chip
p = prob. (a transistor is faulty)
Pf = prob. (the chip is faulty)
Pf = 1- (1- p)
N
If p = 10
-6
N = 10
6


Pf = 63.2%
VLSI Testing NCKUEE-KJLEE
Introduction.8
Introduction
Integrated Circuits (ICs) have
grown in size and complexity
since the late 1950s
Small Scale Integration (SSI)
Medium Scale Integration (MSI)
Large Scale Integration (LSI)
Very Large Scale Integration
(VLSI)
Moores Law: scale of ICs
doubles every 18 months
Growing size and complexity
poses many and new testing
challenges
VLSI
LSI
M
S
I
S
S
I
VLSI Testing NCKUEE-KJLEE
Introduction.9
Importance of Testing
Moores Law results from decreasing feature
size (dimensions)
from 10s of m to 10s of nm for transistors and
interconnecting wires
Operating frequencies have increased from
100KHz to several GHz
Decreasing feature size increases probability
of defects during manufacturing process
A single faulty transistor or wire results in faulty IC
Testing required to guarantee fault-free products
VLSI Testing NCKUEE-KJLEE
Introduction.10
Difficulties in Testing
Fault may occur anytime
- Design
- Process
- Package
- Field
Fault may occur at any place
VLSI circuit are large

- Most problems encountered in testing are NP-complete

I/O access is limited
Vss
Vdd
VLSI Testing NCKUEE-KJLEE
Introduction.11
How to do testing
Circuit modeling
Fault modeling

Logic simulation
Fault simulation
Test generation

Design for test
Built-in self test

Synthesis for testability
Modeling
ATPG
Testable design
From designers point of view:
VLSI Testing NCKUEE-KJLEE
Introduction.12
Circuit Modeling
Structural model--- collection of
interconnected components or elements
Functional model--- logic function
- f(x1,x2,...)=...
- Truth table
Behavioral model--- functional + timing
- f(x1,x2,...)=... , Delay = 10
A
B
E
0
C
D
F
G
1
1
0
0
VLSI Testing NCKUEE-KJLEE
Introduction.13
Levels of Structural Description
Switch level
Higher/ System level
Circuit level
Gate level
B
E
C
1
C
2
C
3
C
4
C
E
C
D
F
G
A
B
VDD VDD VDD
VLSI Testing NCKUEE-KJLEE
Introduction.14
Fault Modeling
The effects of physical defects
Most commonly used fault model: Single stuck-at
fault

A
B
C
D
E
F
G
A s-a-1
A s-a-0
E s-a-1
E s-a-0
D s-a-1
D s-a-0
C s-a-1
C s-a-0
B s-a-1
B s-a-0
F s-a-1
F s-a-0
G s-a-1
G s-a-0
14 faults
Other fault models:
- Break faults, Bridging faults, Transistor stuck-open faults,
Transistor stuck-on faults, Delay faults

VLSI Testing NCKUEE-KJLEE
Introduction.15
Fault Coverage (FC)
FC =
# faults detected
# faults in fault list
a
b
c
6 stuck-at faults
( a
0
,a
1
,b
0
,b
1
,c
0
,c
1
)
Test faults detected FC
{(0,0)}
{(0,1)}
{(1,1)}
{(0,0),(1,1)}
{(1,0),(0,1),(1,1)}
c
1
a
1
,c
1
a
0
,b
0
,c
0
a
0
,b
0
,c
0
,c
1
all
16.67%
33.33%
50.00%
66.67%
100.00%
Example:
0
0
0
1
1
1
1
0
0
VLSI Testing NCKUEE-KJLEE
Introduction.16
Wafer Yield (Chip Yield, Yield)
Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77
Wafer
Defects
Good Chip
Faulty Chip
VLSI Testing NCKUEE-KJLEE
Introduction.17
Testing and Quality
Quality of shipped parts is a function of yield
Y and the test (fault) coverage T
Defect level (DL, reject rate in textbook):
fraction of shipped parts that are defective
IC
Fabrication
Testing
Yield:
Fraction of
good parts
Rejects
Shipped Parts
Quality:
Defective parts
per million (DPM)
VLSI Testing NCKUEE-KJLEE
Introduction.18
Defect Level, Yield & Fault Coverage
Yield (Y)
50%
75%
90%
95%
99%
90%
90%
90%
90%
Fault Coverage (T)
90%
90%
90%
90%
90%
95%
90%
99%
99.9%
DPM (DL)
28,000
67,000
10,000
5,000
1,000
5,000
10,000
1,000
100
DL: defect level

Y: yield
T: fault coverage
DL = 1 - Y
(1-T)

VLSI Testing NCKUEE-KJLEE
Introduction.19
Logic simulation
To determine how a good circuit should work
Given input vectors, determine the normal
circuit response
A
B
E
C
G
F
I
H
D
C
E
C
C
1

B
R
B
I
R
I
F
C
C
2
C
D
E
C
JE
A
B
E
C
D
F
VLSI Testing NCKUEE-KJLEE
Introduction.20
Fault simulation
0
Given a test vector, determine all faults that
are detected by this test vector.
Example:
A
B
C
Test vector (1 1) detects
{ a
0
, b
0
, c
1
}
To determine the behavior of faulty circuits
F
D
B
C
G
1/0
1/0
1
A
1
0
0
1
1
0
1
1
E s.a.0
VLSI Testing NCKUEE-KJLEE
Introduction.21
Test generation
To detect D s-a-0, D must be set to 1.
Thus A=B=1.
To propagate fault effect to the primary output
E must be 1. Thus C must be 0.
Test vector: A=1, B=1, C=0
Given a fault, identify a test to detect this fault
Example:
A
D
B
E
C
F
0 1/0
1
1
1
0
1/0
VLSI Testing NCKUEE-KJLEE
Introduction.22
Automatic Test Pattern Generation
ATPG: Given a circuit, identify a set of test vectors
to detect all faults under consideration.
Input circuit
Form fault list
More faults?
Select a fault
Test generation
Fault simulation
Exit
Fault
dropping
No
Yes
VLSI Testing NCKUEE-KJLEE
Introduction.23
Difficulties in Test Generation
E
B
F
C
A
D
1. Reconvergent fanout
s-a-1
0/1
0
1
1

0
1
1
0
0/1
Cannot detect the fault
Fault detected
VLSI Testing NCKUEE-KJLEE
Introduction.24
Difficulties in Test Generation (cont.)
2. Sequential test generation
J
K
CK
Y
PIs POs
clk
Combinational part
Y
VLSI Testing NCKUEE-KJLEE
Introduction.25
Testable Design
Design for testability (DFT)
ad hoc techniques
Scan design
Boundary Scan

Built-In Self Test (BIST)
Random number generator (RNG)
Signature Analyzer (SA)

Synthesis for Testability
VLSI Testing NCKUEE-KJLEE
Introduction.26
Example of ad hoc Techniques
Insert test points
MUX
T/N
VLSI Testing NCKUEE-KJLEE
Introduction.27
Scan Design
Combinational
logic
PIs POs
FF
FF
FF
Combinational
logic
PIs POs
SFF
SFF
SFF
SO
SI
T/N
Original design
Modified design
VLSI Testing NCKUEE-KJLEE
Introduction.28
Scan Cell Design
DI
DI
D Q
CK
DI
D Q
Q,SO
SI
CK
N/T
(SE)
DI
Q,SO
SI
F
T
F
F
T
F +
Q
F
F
Q
Most cell libraries now have scan cells!
VLSI Testing NCKUEE-KJLEE
Introduction.29
Scan Register
D Q
SI
D Q
SI
D Q
SI
D Q
SI
SO
CLK
SE
Combinational
Circuits

VLSI Testing NCKUEE-KJLEE
Introduction.30
Boundary Scan
Instruction register

Bypass register
M
U
X
T
A
P
Misc. registers
TRST*
TMS
TCK
TDO
I/O Pad
Boundary scan cell Boundary scan path
APPLICATION LOGIC
BIST register
Scan register
TRST*:Test rest (Optional)
TDI: Test data input
TD0: Test data output
TCK: Test clock
TMS: Test mode select
TDI
Sout
Sin
VLSI Testing NCKUEE-KJLEE
Introduction.31
Boundary Scan (Cont.)
Instruction register

Bypass register
M
U
X
T
A
P
Misc. registers
TRST*
TMS
TCK
TDO
APPLICATION LOGIC TDI Sout
Sin
Instruction register

Bypass register
M
U
X
T
A
P
Misc. registers
TRST*
TMS
TCK
TDO
APPLICATION LOGIC
Scan register
TDI Sout
Sin
Instruction register

Bypass register
M
U
X
T
A
P
Misc. registers
TRST*
TMS
TCK
TDO
APPLICATION LOGIC
BIST register
Scan register
TDI Sout
Sin
Instruction register

Bypass register
M
U
X
T
A
P
Misc. registers
TRST*
TMS
TCK
TDO
APPLICATION LOGIC
BIST register
Scan register
TDI Sout
Sin
BIST register
Scan register
BIST register
VLSI Testing NCKUEE-KJLEE
Introduction.32
Places the job of device testing inside the device
itself
Generates its own stimulus and analyzes its own
response
circuit
under test
mux
from system
p
a
t
t
e
r
n

g
e
n
e
r
a
t
o
r

BIST
Controller
biston
R
e
s
p
o
n
s
e

A
n
a
l
y
z
e
r

to system
good/fail
bistdone
Built-In-Self Test (BIST)
VLSI Testing NCKUEE-KJLEE
Introduction.33
Built-In-Self Test (BIST) (Cont.)
F/F
Two major tasks
- Test pattern generation
- Test result compaction

Usually implemented by linear feedback
shift register
F/F F/F
VLSI Testing NCKUEE-KJLEE
Introduction.34
Random Number Generator (RNG)
0001
1000
0100
0010
1001
1100
0110
1011
0101
1010
1101
1110
1. Generate pseudo random patterns
2. Period is 2
n
- 1
1111
0111
0011
0001
(repeat)

F/F F/F F/F F/F
VLSI Testing NCKUEE-KJLEE
Introduction.35
Signature Analyzer (SA)

5 4 2
1 x x x x P
Input sequence 10101111 (8 bits)
1 2 3 4 5
+
Z
Remainder
Quotient


Time Input stream Register contents Output stream
0
1
.
.
5
6
7
8
1 0 1 0 1 1 1 1 0 0 0 0 0 Initial state
1 0 1 0 1 1 1 1 0 0 0 0
. .
. .
1 0 1 0 1 1 1 1
1 0 0 0 0 1 0 1
1 0 0 0 0 1 0 1
0 0 1 0 1 1 0 1
+ +

4 2
x x x R
2
1 x

7 6 5 4 2
1 x x x x x x G
VLSI Testing NCKUEE-KJLEE
Introduction.36
Signature Analyzer (SA) (cont.)
A LFSR performs polynomial division








Probability of aliasing error = 1/2
n
(n: # of FFs)

1 :
1 :
2
2 4 5


x x Q
x x x x P
1
1
5 6 7
2 4 5 2 4 6 7


x x x
x x x x x x x
x G x x x x x x R x Q x P 1
2 4 5 6 7
VLSI Testing NCKUEE-KJLEE
Introduction.37
Memory BIST Architecture
Memory
Module
di
addr
wen
data
sys_di
sys_addr
sys_wen
Memory
Module
rst_l
clk
hold_l
test_h
si
se
data
q
so
Before After
VLSI Testing NCKUEE-KJLEE
Introduction.38
Memory BIST Architecture (Cont.)
BIST Circuitry
Memory
Module
A
l
g
o
r
i
t
h
m
-
B
a
s
e
d

P
a
t
t
e
r
n

G
e
n
e
r
a
t
o
r

C
o
m
p
r
e
s
s
o
r

di
addr
wen
data
compress_h
sys_addr
sys_d
i
sys_wen
rst_l
clk
hold_l
test_h
q
so
clk
rst
si
se
VLSI Testing NCKUEE-KJLEE
Introduction.39
CPU Test Control Architecture
TDI
TCK
compressor
Scan_i
Scan_en
Bist
control
Memory
logic
Scan_o
Scan path
clk
rst_l
TAP Controller
IR
scan
decoder
decoder
bist
decoder
mbist int_scan
bist_se
test_h
hold_l
bist_so
TMS
TDO
VLSI Testing NCKUEE-KJLEE
Introduction.40
Problems re-thinking
A 32-bit adder --- ATPG
A 32-bit counter --- Design for testability + ATPG
A 32MB Cache memory --- BIST
A 10
7
-transistor CPU --- All test techniques
An SOC
VLSI Testing NCKUEE-KJLEE
Introduction.41
Conclusions
Testing is becoming a major factor in design optimization
Conventionally, the designer often optimize one of the three
attributes: speed, area, and power.
At present, a fourth attribute is considered: Testability.
Two major fields in testing
ATPG
--- Fault simulation
--- Test generation
Testable design
--- Design for testability
--- Built-in self-test
--- Synthesis for testability