Vlsi Testability

Technical University Tallinn, ESTONIA
Overview: Testability Evaluation

Outline
Quality Policy of Electronic Design
Tradeoffs of Design for Testability
Testability measures
Heuristic measures
Probabilistic measures
Calculation of testability
Parker - Mc Cluskey method
Cutting method
Conditional probabilities based method

Raimund Ubar
Quality Policy
Yield
2
For example 60%, other chips are faulty
Testimine
Defect level
How many chips from
hundred escape?
Chips from
manufactory
Introduction: The Problem is Money?
Cost of
testing
Quality
Cost of quality
Cost
Cost of
the fault
100%
0%
Optimum
test / quality
How to succeed?
Try too hard!
How to fail?
Try too hard!
(From American Wisdom)
Conclusion:
The problem of testing
can only be contained
not solved
T.Williams
Time
F
a
u
l t C
o
v
e
r
a
g
e
Test
coverage
function
Time
Design for Testability
The problem is - QUALITY:
Quality policy
Yield (Y)
P,n
Defect level (DL)
P
a

Design for testability
Testing
P

- probability of a defect
n - number of defects
P
a
- probability of accepting
a bad product
n
P Y ) 1 ( =
- probability of producing a good product
The problem is - QUALITY:
Quality policy
Yield (Y)
P,n
Defect level (DL)
P
a

n - number of defects
m - number of faults tested
P

- probability of a defect
P
a
- probability of accepting a bad product
T - test coverage

) 1 (
) 1 (
1 1 1 ) 1 ( 1
) 1 (
T
n
m
n
m n
m n
a
n
a
Y Y Y P
P P
P
DL

= = = =
+
=
n m
a
P P P ) 1 ( ) 1 ( =
n
P Y ) 1 ( =
The problem is - Money:
Y(%)
T(%)
10
10
50
90
50 90
8 5 1
45 25 5
81 45 9
) 1 (
1
T
Y DL

=
Goal: DL + T | Testability |
Paradox: Testability | DL | (Y +)
DL
T(%)
Y+
100 0
1
Tradeoffs:
DFT: Resynthesis or
adding extra hardware
Performance +
Logic complexity |
Area |
Number of I/O |
Power consumption |
Yield +
Economic tradeoff:
C (Design + Test) < C (Design) + C (Test)
Goal: DL + T | Testability |
Paradox: Testability | DL | (Y +)
Economic tradeoff:
C (Design + Test) < C (Design) + C (Test)
C (DFT) + C (Test) < C (Design) + C (Test)
Test generation
Testing
Troubleshooting
Volume
C (Test) = C
TGEN
+ (C
APLIC
+ (1 - Y) C
TS
) Q

C (DFT) = (C
D
+ C
D
) + Q(C
P
+ C
P
)
Design
Product
Testability Criteria
Qualitative criteria for Design for testability:
Testing cost:
Test generation time
Test application time
Fault coverage
Test storage cost (test length)
Availability of Automatic Test Equipment
Redesign for testability cost:
Performance degradation
Area overhead
I/O pin demand

Testability of Design Types
General important relationships:
- T (Sequential logic) < T (Combinational logic)
Solutions: Scan-Path design strategy
- T (Control logic) < T (Data path)
Solutions: Data-Flow design, Scan-Path design strategies
- T (Random logic) < T (Structured logic)
Solutions: Bus-oriented design, Core-oriented design
- T (Asynchronous design) < T (Synchronous design)

T (Sequential logic) < T (Combinational logic
Combinationa
l circuit
IN OUT
R q
q
Combination
al circuit
IN OUT
R
Scan-IN
Scan-OUT
q
q
Solution: Scan-Path design strategy

T (Control logic) < T (Data path)
Solutions:
Scan-Path design strategie
Data-Flow design

M
3
e
+
M
1
a
*
M
2
b
-
-
R
1
IN
-
-
-
c
d
y
1
y
2 y
3
y
4
Control Part
R
2
Data Part
Raimund Ubar
13
How to test million transistors?
Scan-Path Based Testing
Multi Site Test
ATE
H.-J.Wunderlich, U Stuttgart
All memory components are made
transparent via shift registers
Test
patterns
Response
Test
System
Fault
T (Random logic) < T (Structured logic)
Solutions: Bus-oriented design, Core-oriented design

System
16 bit
counter
&
1
Sequence of
2
16
bits
Sea of gates
Testability Estimation Rules of Thumb
Circuits less controllable
Decoders
Circuits with feedback
Counters
Clock generators
Oscillators
Self-timing circuits
Self-resetting circuits

Circuits less observable
Circuits with feedback
Embedded
RAMs
ROMs
PLAs
Error-checking circuits
Circuits with redundant
nodes

Bad Testability: Fault Redundancy
1
&
&
&
1
&
x
1

x
2

&
x
4

x
3

y
0
) (
2
4 3 4 2 1 1
c
c
v v v =
x
y
x x x x x x y
Faults at x
2
is not testable
Optimized function:
Internal signal dependencies:
1
&
&
1
1
1
1
1
Impossible pattern,
OR XOR is not testable
3 4 1
x x x y v v =
Redundant gates (bad design):
CREDES Summer School
Raimund Ubar
Fault Redundancy
1
&
&
&
1
1
01
10
01
1
Hazard control circuit:
Redundant AND-gate
Fault 0 is not testable
1
0
Error control circuitry:
Decoder

1
E = 1 if decoder is fault-free
Fault 1 is not testable
E=1
17
101
Hazard
Raimund Ubar
Fault Redundancy
0
) (
2
4 3 4 2 1 1
c
c
v v v =
x
y
x x x x x x y
Faults at x
2
are
not testable, the
node is redundant
1
&
&
&
1
&
x
1

x
2

&
x
4

x
3

y
Redundant gates
(bad design):
1
42
42 3 41 12 11
=
c
c
v v =
x
y
x x x x x y
if 0
4
= x
Fault x
42
0 is not testable
x
11

1
&
&
&
x
1

&
x
4

x
3

y
x
41

x
42

x
12

18
Raimund Ubar
Fault Redundancy
Redundant gates
(bad design):
1
&
&
&
x
1

&
x
4

x
3

y
1
42
42 3 41 12 11
=
c
c
v v =
x
y
x x x x x y
if 0
4
= x
Fault x
42
0 is not testable
x
41

x
42

x
11

x
12

1
&
&
x
1

x
3

y
x
4

x
11

x
12

1
12
3 41 12 11
=
c
c
v v =
x
y
x x x x y
Fault x
12
1 is not testable
if
1
1
= x
3 4 1
x x x y v v =
Final result of optimization:
1
x
3

y
x
1

x
4

19
Testability Measures
Evaluation of testability:
- Controllability
- C
0
(i)
- C
1
(j)
- Observability
- O
Y
(k)
- O
Z
(k)
- Testability

1
2
20
&
&
1
2
20
1
x
Defect
Probability of detecting 1/2
60

1
2
20
&
1
2
20
1
i
k
j
Y
Z
Controllability for 1 needed
Heuristic Testability Measures
Controllability calculation: AND gate
Measure: minimum number of nodes that must be set to produce 0
For inputs: C
0
(x) = C
1
(x) = 1
For other signals: recursive calculation starting from inputs
C
0
(x
i
) = 23
C
0
(x
j
) = 11
&
C
0
(x
k
) =
C
0
(x
1
) = 1
C
0
(x
2
) = 1
min [C
0
(x
i
), C
0
(x
j
) ] + 1 =
= min (23,11) + 1 = 12
Controllability calculation: OR gate
For inputs: C
0
(x) = C
1
(x) = 1
C
0
(x
i
) = 23
C
0
(x
j
) = 11
1
C
0
(x
k
) =
C
0
(x
1
) = 1
C
0
(x
2
) = 1
C
0
(x
i
) + C
0
(x
j
) + 1 =
= 23 + 11 + 1 = 35
Controllability calculation:
For inputs: C
0
(x) = C
1
(x) = 1
C
1
(x
i
) = 23
C
1
(x
j
) = 11
&
C
1
(x
k
) = C
1
(x
i
) + C
1
(x
j
) + 1 =
= 23 + 11 + 1 = 35
C
1
(x
1
) = 1
C
1
(x
2
) = 1
Controllability calculation: EXOR gate
Measure: minimum number of nodes that must be set in order to produce 0
For inputs: C
0
(x) = C
1
(x) = 1
C
0
(x
i
) = 23
C
1
(x
i
) = 18

C
0
(x
k
) = min { [ C
0
(x
i
) + C
0
(x
j
) ],
[C
1
(x
i
) + C
1
(x
j
) ] } + 1 =
min{ (23 +12), (18 + 20) } + 1 =
min (35,38) + 1 = 36
C
0
(x
1
) = 1
C
0
(x
2
) = 1
C
0
(x
j
) = 12
C
1
(x
j
) = 20
Measure: minimum number of nodes that must be set in order to produce 0 or 1
For inputs: C
0
(x) = C
1
(x) = 1
For other signals: recursive calculation rules:
&
x y
&
x
1

y
x
2

1
x
1

y
x
2

x
1

y
x
2

C
0
(y) = min{C
0
(x
1
), C
0
(x
2
)} + 1
C
1
(y) = C
1
(x
1
) + C
1
(x
2
) + 1
C
0
(y) = C
1
(x) + 1
C
1
(y) = C
0
(x) + 1
C
1
(y) = min{C
1
(x
1
), C
1
(x
2
)} + 1
C
0
(y) = C
0
(x
1
) + C
0
(x
2
) + 1
C
0
(y) = min{(C
0
(x
1
) + C
0
(x
2
)), (C
1
(x
1
) + C
1
(x
2
))} + 1
C
1
(y) = min{(C
0
(x
1
) + C
1
(x
2
)), (C
1
(x
1
) + C
0
(x
2
))} + 1
Observability calculation:
Measure: minimum number of nodes which must be set for fault propagating
For outputs: O(y) = 1
O(x
i
) = O(x
k
) + C
1
(x
j
) =
= 23 + 11 + 1 = 35
C
1
(x
j
) = 11
&
O(y) = 1
O(x
k
) = 23
Observability calculation:
Measure: minimum number of nodes which must be set for fault propagating
For outputs: O(y) = 1
&
x y
&
x
1

y
x
2

1
x
1

y
x
2

x
1

y
x
2

O(x
1
) = O(y) + C
1
(x
2
) + 1
O(x) = O(y) + 1 O(x
1
) = O(y) + C
0
(x
2
) + 1
O(x
1
) = O(y) + 1
Testability calculation:
Measure: sum of controllability and observability
O(x
i
) = 35
C
1
(x
j
) = 11
&
O(y) = 1
O(x
k
) = 23
T(x 0) = C
1
(x) + O(x)
T(x 1) = C
0
(x) + O(x)
T(x
i
= 0) = O(x
i
) + C
1
(x
j
) = 35 + 16 = 51
C
1
(x
i
) = 16
Controllabilies Obs.
x C
0
(x) C
1
(x) O(x)
1 1 1 10
2 1 1 12
3 1 1 11
4 1 1 11
5 1 1 10
6 1 1 10
7 3 2 9
7
1
3 2 11
7
2
3 2 9
7
3
3 2 9
a 4 2 9
b 4 2 7
c 4 2 7
d 4 2 7
e 5 5 4
y 8 5 1

Controllability and observability:
&
&
&
&
&
&
&
1
2
3
4
5
6
7
7
1

7
2

7
3

a
b
c
d
e
y
Macro
Controllabilies Obs. Testab.
x C
0
(x) C
1
(x) O(x) T(x0)
1 1 1 10 11
2 1 1 12 13
3 1 1 11 12
4 1 1 11 12
5 1 1 10 11
6 1 1 10 11
7 3 2 9 11
7
1
3 2 11 13
7
2
3 2 9 11
7
3
3 2 9 11
a 4 2 9 11
b 4 2 7 9
c 4 2 7 9
d 4 2 7 9
e 5 5 4 9
y 8 5 1 6

Testability calculation:
&
&
&
&
&
&
&
1
2
3
4
5
6
7
7
1

7
2

7
3

a
b
c
d
e
y
Macro
T(x 0) = C
1
(x) + O(x)
T(x 1) = C
0
(x) + O(x)
Probabilistic Testability Measures
Measure: probability to produce 0 or 1 at the given nodes
For inputs: C
0
(i) = p(x
i
=0) = 1 - p
xi
C
1
(i) = p(x
i
=1) = 1 - p(x
i
=0) = p
xi

&
x y
&
x
1

y
x
2

1
x
1

y
x
2

p
y
= p
x1
p
x2

p
y
= 1 - p
x

p
y
= 1 - (1 - p
x1
)(1 - p
x2
)
&
x
1

y
x
n

.
.
.

xi
n
i
y
p p
H
=
=
1
1
x
1

y
x
n

.
.
.

) 1 ( 1
1
xi
n
i
y
p p =
H
=
Probabilities of reconverging fanouts:

x
1

y
x
2

p
y
= 1 - (1 - p
a
) (1 - p
b
)
= 1 - 0,75*0,75 = 0,44
&
x
1

y
x
2

&
1
a
b
&
x
y p
y
= p
x
p
x
= p
x
2
?

Signal correlations:
p
y
= (1 p
x1
) p
x2
+ (1 p
x2
) p
x1

= 0,25 + 0,25 = 0,5
Calculation of Signal Probabilities
&
x
1

y
x
2

&
1
p
y
= 1 - (1 - p
a
) (1 - p
b
) =
= 1 - (1 - p
x1
(1 - p
x2
))(1 - p
x2
(1 - p
x1
)) =
= 1 - (1 - p
x1
+ p
x1
p
x2
) (1 - p
x2
+ p
x1
p
x2
) =
= 1 (1 - p
x2
+ p
x1
p
x2
- p
x1
+ p
x1
p
x2
- p
2
x1
p
x2
+
+ p
x1
p
x2
- p
x1
p
2
x2
+ p
2
x1
p
2
x2
) =
= 1 (1 - p
x2
+ p
x1
p
x2
- p
x1
+ p
x1
p
x2
- p
x1
p
x2
+
+ p
x1
p
x2
- p
x1
p
x2
+ p
x1
p
x2
) =
= p
x2
- p
x1
p
x2
+ p
x1
- p
x1
p
x2
+ p
x1
p
x2
-
- p
x1
p
x2
+ p
x1
p
x2
- p
x1
p
x2
) =
= p
x1
+ p
x2
- 2p
x1
p
x2
= 0,5

a
b
Parker - McCluskey
algorithm:
Straightforward methods:
&
&
&
a
c
y
&
b
1
2
3
2
1
2
2
2
3
Parker - McCluskey algorithm:
p
y
= p
c
p
2
= (1- p
a
p
b
) p
2
=
= (1 (1- p
1
p
2
) (1- p
2
p
3
)) p
2
=
= p
1
p
2
2
+ p
2
2
p
3

- p
1
p
2
3
p
3
=
= p
1
p
2

+ p
2

p
3

- p
1
p
2
p
3
= 0,38
Calculation gate by gate:
p
a
= 1 p
1
p
2
= 0,75,
p
b
= 0,75, p
c
= 0,4375, p
y
= 0,22
For all inputs: p
k
= 1/2
Parker-McCluskey:
&
&
&
a
c
y
&
b
1
2
3
2
1
2
2
2
3
Observability:
p(cy/ca = 1) = p
b
p
2
=
= (1 - p
2
p
3
) p
2
= p
2
- p
2
2
p
3

= p
2

- p
2
p
3

= 0,25
x
Testability:
p(a 1) = p(cy/ca = 1) (1 - p
a
) =
= (p
2

- p
2
p
3
)(p
1
p
2
) =
= p
1
p
2
2

- p
1
p
2
2
p
3
=
= p
1
p
2

- p
1
p
2
p
3

= 0,125
For all inputs: p
k
= 1/2
Idea:
Complexity of exact
calculation is reduced by
using lower and higher
bounds of probabilities
Technique:
Reconvergent fan-outs are
cut except of one
Probability range of [0,1] is
assigned to all the cut lines
The bounds are propagated
by straightforward
calculation
Cutting method
&
&
&
&
&
&
&
1
2
3
4
5
6
7
7
1

7
2

7
3

a
b
c
d
e
y
Lower and higher bounds for the
probabilities of the cut lines:
p
71
:= (0;1), p
72
:= (0;1), p
73
:= 0,75
For all inputs:
p
k
= 0,5
Reconvergent
fan-outs are cut
except of one
7
1
and 7
2
Probability
range of [0,1] is
assigned to all
the cut lines -
7
1
and 7
2

The bounds are
propagated by
straightforward
calculation

Cutting method
&
&
&
&
&
&
&
1
2
3
4
5
6
7
7
1

7
2

7
3

a
b
c
d
e
y
p
k
[p
LB
, p
HB
) Exact p
k
p
k
[p
LB
, p
HB
) Exact p
k
p
7
3/4 3/4 p
b
[1/2, 1] 5/8
p
71
[0, 1] 3/4 p
c
5/8 5/8
p
72
[0, 1] 3/4 p
d
[1/2, 3/4] 11/16
p
73
3/4 3/4 p
e
[1/4, 3/4] 19/32
p
a
[1/2, 1] 5/8 p
y
[34/64, 54/64 ] 41/64
Calculation steps:
1/2
[0,1]
[1/2,1]
3/4
3/4
1/2
1/2
5/8
[1/2,1]
[1/2,3/4]
[1/4,3/4]
[34/64,54/64]
Exact value:
41/64
Method of conditional
probabilities
y
x
P(y) = p(y/x=0) p(x=0) + p(y/x=1) p(x=1)
e
= = =
) 1 , 0 (
) ( ) /( ( ) (
i
i x p i x y p y p
Probabilitiy for y
Conditions x e set of conditions
Conditional probabilitiy
Idea of the method:
Two conditional probabilities are calculated along the paths (NB! not bounds as in
the case of the cutting method)
Since no reconvergent fanouts are on the paths, no danger for signal correlations
Method of conditional
probabilities
&
&
&
&
&
&
&
1
2
3
4
5
6
7
7
1

7
2

7
3

a
b
c
d
e
y
e
= = =
) 1 , 0 (
) ( ) /( ( ) (
i
i x p i x y p y p
y
x
NB! Probabilities
P
k
= [P
k
*
= p(x
k
/x
7
=0), P
k
**
= p(x
k
/x
7
=1)]
are propagated, not bounds
as in the cutting method.
For all inputs: p
k
= 1/2
P
k
[P
k
*
, P
k
**
] P
k
[P
k
*
, P
k
**
]
P
7
P
b
[1, 1/2]
P
71
P
c
[1, 1/2]
P
72
P
d
[1/2, 3/4]
P
73
P
e
[1/2, 5/8]
P
a
[1, 1/2] P
y
[1/2, 11/16 ]
3/4
[1,1/2]
[1,1/2]
[1,1/2]
[1/2,3/4]
[1/2,5/8]
[1/2,11/16]
p
y
= p(y/x
7
=0)(1 - p
7
) + p(y/x
7
=1)p
7
= (1/2 x 1/4) + (11/16 x 3/4) = 41/64
Using BDDs:
1
2
1

3

2
3
3
y
L
1

L
2

p
y
= p(L
1
) + p(L
2
) =
= p
1
p
21
p
23
+ (1 - p
1
) p
22
p
3
p
23
=
= p
1
p
2
+ p
2
p
3
- p
1
p
2
p
3
= 0,38

&
&
&
a
c
y
&
b
1
2
3
2
1
2
2
2
3
For all inputs: p
k
= 1/2
p
1
p
21
p
23

(1-p
1
)p
22
p
3
p
23

2

y
p
2
p
1

p
2
(1-p
1
)p
3

1
2
2

Calculating Probabilities on BDDs
&
&
&
a
c
y
&
b
1
2
3
2
1
2
2
2
3
1
2
1
2
2
2
3
3
y
L
1
L
2
p
y
= E H p
x

L
k
eL(1) xeX
k

Example:

L
1
= (1,2
1
,2
3
)
L
2
= (1,2
2
,3,2
3
)

p
y
= p
1
p
2

+ p
1
p
2
p
3
= 0,375
Heuristic and Probabilistic Measures
p
y
= E H p
x

k: L
k
eL(1) xeX
k
CC
1
[y] = min { E CC
1
(x(m) } + const.
k: l
k
eL(1) meM
k

Heuristic controllability measure:
Probabilistic measure:
1
2
1
2
2
2
3
3
y
L
1
L
2
Heuristic Controllabilities
Using BDDs for controllability
calculation:
&
&
&
a
c
y
&
b
1
2
3
2
1
2
2
2
3
x C
0
(x) C
1
(x)
a 3 2
b 3 2
c 5 4
y 2 6
Gate level calculation
1 2
1

2
2
2
3
3
y
L
1

L
2

3 3 1
3 3
BDD-based algorithm
for the heuristic
measure is the same
as for the
probabilistic measure
C
1
(y) = min [(C
1
(L
1
), C
1
(L
2
)] + 1 =
= min [C
1
(x
1
) + C
1
(x
2
),
C
0
(x
1
) + C
1
(x
2
) + C
1
(x
3
)] + 1 =
= min [2, 3] + 1 = 3
Using BDDs:
1 2
1

2
2
2
3
3
y
L
1
L
2

Observability:
p(cy/cx
21
= 1) = p(L
1
) p(L
2
) p(L
3
) =
= p
1
p
23
(1 - p
3
) = 0,125
&
&
&
a
c
y
&
b
1
2
3
2
1
2
2
2
3
x
L
3

Testability:
p(x
21
0) = p
21
p(cy/cx
21
= 1) =
= p
21
p(L
1
) p(L
2
) p(L
3
) =
= p
2
p
1
(1 - p
3
) = 0,125
Why: p(cy/cx
21
= 1) = p
21
p(cy/cx
21
= 1)?
Calculating Observabilities on BDDs
&
&
&
&
&
&
&
1
2
3
4
5
6
7
7 1
7 2
7 3
a
b
c
d
e
y
Macro
cy/cx(m) = L(m
0
,m) . L(m
1
, m
T,1
) . L(m
0
, m
T,0
)

p(cy/cx(m)=1)=p(m
0
,m) . p(m
1
,m
T,1
) . p(m
0
,m
T,0
)
6 7 3
1
2
5
7 2 7 1
y
Calculating Observabilities on BDDs
6 73
5 2
2
5
2
2
5 2
2
5
2
2
6
7
1
72
1/64
1/64
1/64
1/64
4/64
1/64
1/64
1/64
&
&
&
&
&
&
&
1
2
3
4
5
6
7
7 1
7 2
7 3
a
b
c
d
e
y
Macro
6 7 3
1
2
5
7 2 7 1
y
Calculation procedure:
p(cy/cx
1
= 1) = 11/64
Combining BDDs and conditional probabilities
x
z
y
w
Using BDDs gives correct results only inside the blocks,
not for the whole system
New method:
Block level: use BDDs and straightforward calculation
System level: use conditional probabilities
Register Transfer Level and DDs
Superposition of word-level DDs:
R
2
M
3
e
+
M
1
a
*
M
2
b
-
-
R
1
IN
-
-
-
c
d
y
1
y
2 y
3
y
4
y4
y3 y1
R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2
0
1
2
0
1
0
1
0
1
#0
R2
IN
R1
2
3
Calculating RT-Level Observabilities
p
y
= E H p
x

L
k
eL(1) xeX
k

Gate-level calculation:
RT-level calculation:
Example:
P(R
2
=R
1
- R
2
) = P(y
4
=2) P(y
3
=3) P(y
2
=0)
Terminal nodes
data-path):
y 4
y 3 y 1
R 1 + R 2
IN + R 2
R 1 * R 2
IN* R 2
y 2
R 2
0
1
2
0
1
0
1
0
1
#
0
R 2
IN
R 1
2
3
P(y=z(m
T
)) = E H P(x=e)

L
i
eL(m
0
,m
T
) xeX
i

Calculating RT-level Probabilities
p
y
= p(y=1) = E H p
x

L
k
eL(1) xeX
k

3,4
0 2
q
1
0 1
0
q
' #
1
#
4 x
A
#
2
1
#
5 x
B
#
3
Gate-level calculation:
RT-level calculation:
P(y=k) = E H P(x=e)

L
i
eL(k) xeX
i
Example:
P(q=5) = P(q=2)P(x
B
=0) + P(q=3) + P(q=4)
Nonterminal nodes
(control-path):

Vlsi Testability

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Technical University Tallinn, ESTONIA

Overview: Testability Evaluation

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