COMPUTER ARCHITECTURE COMPUTER AIDED DESIGN - CAD Primary approaches to IC chip design: Mask-programmable ICs A ROM that can be programmed using standard PROM programmer without specialized software or hardware. Disadvantages: Consume more power Slower than dedicated logic circuit OBE TECHNIQUE: LUCK OF THE DRAW STUDENTS Standard-cell devices In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology (the general class to which standard cells belong) makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect.
Along with semiconductor manufacturing advances, standard cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi- million gate system-on-a-chip (SoC) devices.
PLD A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a circuit it must be programmed. For bigger logic circuits, complex PLDs or CPLDs can be used. CPLDs can replace thousands, or even hundreds of thousands, of logic gates. As of 2005, most CPLDs are electrically programmable and erasable, and non- volatile VHDL Many PAL programming devices accept input in a standard file format, commonly referred to as 'JEDEC files'.They are analogous to software compilers. The languages used as source code for logic compilers are called hardware description languages, or HDLs. PALASM and ABEL are frequently used for low-complexity devices, while Verilog and VHDL are popular higher-level description languages for more complex devices. The more limited ABEL is often used for historical reasons, but for new designs VHDL is more popular, even for low- complexity designs.
SCHEMATIC LOGIC DESIGN USING CPLD Overview A schematic design defines the functionality of a logic circuit using one or more schematic files, such as gates, flip-flops and building-block functions similar to 74xx TTL devices. Schematics can also contain "custom" symbols for which you define the functionality using behavioral moduls. Design Flow Summary
The Design Manager/Flow Engine takes EDIF netlist, XNF or PLD files from your design tool and fits them onto devices. You can select a specific device or let the Design Manager select a device for you, based on the most economical solution that will satisfy the functional and timing parameters of the design.
GENERATED REPORTS By default the fitter produces the following significant output files: Fitting report (design_name.rpt) lists summary and detailed information about the logic and I/O pin resources used by the design, including the pinout, error and warning messages, and Boolean equations representing the implemented logic. Static timing report (design_name.tim) shows a summary report of worst-case timing for all paths in the design; optionally includes a complete listing of all delays on each individual path in the design. Guide file (design_name.gyd) contains all resulting pinout information required to reproduce the current pinout if the pinfreeze option is specified during the next invocation of the cpld command for the same design name. (The Guide file is written only upon successful completion of the fitter.) Programming file (design_name.jed for XC9000) is a JEDECformatted (9k) programming file to be down-loaded into the cpld device. Timing simulation database (design_name.nga) a binary database representing the implemented logic of the design, including all delays. SIMULATION CONCEPT Timing Simulation The Design Manager optionally produces timing simulation data when you implement your design, and produces either an EDIF, VHDL or Verilog HDL formatted netlist for your simulator
*VHDL = VHSIC hardware description language *VHSIC = very-high-speed integrated circuits ELEMENT LOGIC IN COMPUTER LOGIC Clock Clock is the frequency of the processor at which its running. The standard unit is hertz (Hz); most people today use GHz and MHz. Generally, within the same CPU series, higher processor clock speed means faster processing time. The technical term for processor clock is the speed, in which a single atomic action can be performed. Hence a 1GHz CPU can evaluate a single NAND 1 billion time a second.
Positive edge triggered Negative edge triggered CLOCK FUNCTION In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Since the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Finally, the control of any differences in the delay of the clock signals can severely limit the maximum performance of the entire system. GATED FLIP-FLOP: SR Flip-flop D Flip-flop Master-slave flip-flop JK Flip-flop OBE TECHNIQUE: ONE MINUTE PAPER FLIP-FLOP In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. Flip-flops and latches are used as data storage elements.
SR FLIP-FLOP Symbol for active high flip-flop Symbol for active low flip-flop SR FLIP-FLOP It can store either a binary number 0 or 1 and the circuit has two states known as SET and RESET. When a flip-flop is flip to the set (where it stores a binary 1) or flop to the reset (where it stores the binary 0), the output of the circuit will remain (Latched / locked) as long as it is been power supplied. SR flip-flop can be construct using both NAND or NOR gates.
NAND GATE ACTIVE LOW NOR GATE ACTIVE HIGH SR FLIP-FLOP Active High SR Flip-flop Active Low SR Flip-flop SR FLIP-FLOP Operation table for active high and active low SR Flip-flop: S R Operation for active high Operation for active low 0 0 hold invalid 0 1 reset set 1 0 set reset 1 1 invalid hold D FLIP-FLOP Logic symbol for D Flip-flop D FLIP-FLOP D flip-flop is known as Delay or Data flip-flop because of its ability to store data and transfer the information after receiving the pulse. It is called the D flip-flop for this reason, since the output takes the value of the D input or data input, and delays it by one clock cycle. D Flip-flop can be constructed using either SR or JK flip-flop by connected with the inverter between the input S and R, or J and K input.
D FLIP-FLOP D flip-flop schematic CLK D Q t+1
0 0 1 1 Truth table for D flip-flop:
MASTER-SLAVE FLIP-FLOP Logic diagram
A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a master and the other as a slave. The master flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter. MASTER-SLAVE FLIP-FLOP When the pulse returns to 0, the master flip- flop is disabled and the slave flip-flop is enabled. The slave flip-flop then goes to the same state as the master flip-flop. Timing relationship in a master slave flip-flop:
JK FLIP-FLOP Logic symbol for JK flip-flop positive edge triggered Logic symbol for JK flip-flop - negative edge triggered JK FLIP-FLOP JK flip-flop operation is similar to the SR flip- flop operation. The only difference is the flip- flop does not have the forbidden or invalid state.
The truth table for both flip-flop are mostly the same, except when the given input of J = K = 1, the flip-flop will be in the toggle state.
Toggle is a condition where the output of a flip- flop will invert from 0 to 1 and vice versa at positive or negative clock edge triggered.
JK FLIP-FLOP Operation table for JK Flip-flop J K Operation 0 0 Hold 0 1 Reset 1 0 Set 1 1 Toggle FLIP-FLOP APPLICATIONS Shift Register Binary Counter Sequence Counter Sequential Magnitude Comparator BCD to Seven Segment Decoder SHIFT REGISTER A shift register is a cascade of flip-flops, sharing the same clock, which has the output of any one but the last flip-flop connected to the data input of the next one in the chain, resulting in a circuit that shifts by one position the one-dimensional bit array stored in it, shifting in the data present at its input and shifting out the last bit in the array, when enabled to do so by a transition of the clock input.
SHIFT REGISTER USING JK FLIP-FLOP SHIFT REGISTER OPERATION Timing Diagram BINARY COUNTER A Counter is a device, which stores (and sometimes displays) the number of times a particular event has occurred, often in relationship to a CLOCK Signal. In electronics, counters can be implemented quite easily using memory devices such as Flip-flops.
COUNTER Kinds of counter Asynchronous (ripple) counter Synchronous counter Decade counter Up/down counter Ring counter Johnson counter ASYNCHRONOUS (RIPPLE) COUNTER Schematic:
An asynchronous (ripple) counter is a single JK- type flip-flop, with its J (data) input fed from its own inverted output. ASYNCHRONOUS (RIPPLE) COUNTER This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0). This counter will increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0. ASYNCHRONOUS (RIPPLE) COUNTER You can continue to add additional flip-flops, always inverting the output to its own input, and using the output from the previous flip-flop as the clock signal. The result is called a ripple counter, which can count to 2 n -1 where n is the number of bits (flip- flop stages) in the counter. SYNCHRONOUS COUNTER A simple way of implementing the logic for each bit of an ascending counter is for each bit to toggle when all of the less significant bits are at a logic high state. For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high; and so on. Synchronous counters can also be implemented with hardware finite state machines, which are more complex but allow for smoother, more stable transitions. Hardware-based counters are of this type.
DECADE COUNTER A decade counter is one that counts in decimal digits, rather than binary. The latter type of circuit finds applications in multiplexers and demultiplexers, or wherever a scanning type of behavior is useful The decade counter is also known as a mod- counter when it counts to ten (0, 1, 2, 3, 4, 5, 6, 7, 8, 9). A Mod Counter that counts to 64 stops at 63 because 0 counts as a valid digit.
UP/DOWN COUNTER A counter that can change state in either direction, under the control of an up/down selector input, is known as an up/down counter.
When the selector is in the up state, the counter increments its value. When the selector is in the down state, the counter decrements the count.
RING COUNTER A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first, that is, in a ring.
Typically, a pattern consisting of a single bit is circulated so the state repeats every n clock cycles if n flip-flops are used.
It can be used as a cycle counter of n states.
JOHNSON COUNTER A Johnson counter (or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a modified ring counter, where the output from the last stage is inverted and fed back as input to the first stage. The register cycles through a sequence of bit- patterns, whose length is equal to twice the length of the shift register, continuing indefinitely. These counters find specialist applications, including those similar to the decade counter, digital-to-analog conversion, etc. They can be implemented easily using D- or JK- type flip-flops. BCD TO 7 SEGMENT DECODER 7-segment LED (Light Emitting Diode) or LCD (Liquid Crystal) displays, provide a very convenient way of displaying information or digital data in the form of numbers, letters or even alpha-numerical characters and they consist of 7 individual LED's (the segments), within one single display package.
7-Segment Display Format TRUTH TABLE FOR A 7-SEGMENT DISPLAY BINARY CODED DECIMAL (BCD) Binary Coded Decimal (BCD or "8421" BCD) numbers are made up using just 4 data bits (a nibble or half a byte). BCD numbers only range from 0 to 9, with the binary number patterns of 1010 through to 1111 (A to F) being invalid inputs for this type of display and so are not used as shown below.
BCD TO 7-SEGMENT DECODER BCD TO 7-SEGMENT DECODER An example of the 4-bit BCD input (0100) representing the number 4 is given below: