Counters

Circuits that can increment or decrement a

count by 1
Designed using T and D flip-flops
Asynchronous Counters:
Up-Counter with T Flip-Flops
Down-Counter with T Flip-Flops
Synchronous Counters:
Synchronous Counter with T Flip-Flop
Synchronous Counter with D Flip-Flop




Counters
Counters with Parallel Load
Normally, initial count being equal to 0
Sometimes it is desirable to start with different
count
Other types of counters:
BCD Counter
Ring Counter
Johnson Counter

Asynchronous Counter
Asynchronous events that do not occur at
the same time
An asynchronous counter is one in which
the flip-flops within the counter do not
change states at exactly the same time
because they do not have a common clock
pulse
Up-Counter with T Flip-Flops
3-bit counter from 0 to 7
Clock inputs are connected in cascade
T input of each flip-flop is connected to
constant 1
Because it counts in the upward direction,
we call it an up-counter

Figure 5.19. A three-bit up-counter.
T Q
Q
Clock
T Q
Q
T Q
Q
1
Q
0
Q
1
Q
2
(a) Circuit
Clock
Q
0
Q
1
Q
2
Count 0 1 2 3 4 5 6 7 0
(b) Timing diagram
Example 1
Implement 3-bit up-counter using JK flip-
flops?
Answer
Down-Counter with T Flip-Flops
Clock inputs of the 2
nd
and 3
rd
flip-flops are
driven by the Q outputs of the preceding
stages
The circuit counts in the sequence
0,7,6,5,4,3,2,1,0,7,6
Because it counts in downward direction,
we call it down-counter
Figure 5.20. A three-bit down-counter.
T Q
Q
Clock
T Q
Q
T Q
Q
1
Q
0
Q
1
Q
2
(a) Circuit
Clock
Q
0
Q
1
Q
2
Count 0 7 6 5 4 3 2 1 0
(b) Timing diagram
Synchronous Counter
Asynchronous counters are simple, but not
very fast
The delays caused by the cascaded clocking
scheme may become too long
We can build a faster counter by clocking
all flip-flops at the same time
synchronous counter
Table 5.1. Derivation of the synchronous up-counter.
0
0
1
1
0
1
0
1
0
1
2
3
0
0
1
0
1
0
4
5
6
1 1 7
0
0
0
0
1
1
1
1
Clock cycle
0 0 8 0
Q
2
Q
1
Q
0
Q
1
changes
Q
2
changes
Synchronous Counter with
T Flip-Flops
Synchronous Counter with
T Flip-Flops
T
0
= 1
T
1
= Q
0
T
2
= Q
0
Q
1
Example 4-bit synchronous up-counter
Instead of using AND gates of increased
size for each stage, we use a factored
arrangement

Figure 5.21. A four-bit synchronous up-counter.
T Q
Q Clock
T Q
Q
T Q
Q
1
Q
0
Q
1
Q
2
(a) Circuit
Clock
Q
0
Q
1
Q
2
Count 0 1 2 3 5 9 12 14 0
(b) Timing diagram
T Q
Q
Q
3
Q
3
4 6 8 7 10 11 13 15 1
Enable & Clear Capability
Often it is desirable to be able to inhibit
counting, so that the count remains in its
present state
This may be accomplished by including an
Enable control signal
The clear inputs on all flip-flops is
necessary to start with the count equal to
zero


Figure 5.22. Inclusion of Enable and Clear capability.
T Q
Q Clock
T Q
Q
Enable
Clear_n
T Q
Q
T Q
Q
Synchronous Counter with
D Flip-Flops
Example - 4-bit up-counter that counts in
the sequence 0, 1, 2, . . . , 14, 15, 0, 1,
and so on
If Enable = 1, D could be expressed as
figure


Figure 5.23. A four-bit counter with D flip-flops.
Counters with Parallel Load
Sometimes it is desirable to start with a
different count
To allow this mode of operation, a counter
circuit must have some inputs through
which the initial count can be loaded
A two-input multiplexer is inserted before
each D input
One input to the multiplexer is used to
provide the normal counting operation
The other input is a data bit that can be
loaded directly into the flip-flop
A control input, Load, is used to choose the
mode of operation
The circuit counts when Load = 0
A new initial value, D
3
D
2
D
1
D
0
, is loaded
into the counter when Load = 1
Counters with Parallel Load
Figure 5.24. A counter with parallel-load capability.
Reset Synchronization
Synchronous reset
AND in the next clock pulse
Asynchronous reset
Clear feature
Example - a modulo-6 counter, for which
the counting sequence is 0, 1, 2, 3, 4, 5, 0, 1,
and so on
Figure 5.25. A modulo-6 counter with synchronous reset.
Enable
Q
0
Q
1
Q
2
D
0
D
1
D
2
Load
Clock
1
0
0
0
Clock
0 1 2 3 4 5 0 1
Clock
Count
Q
0
Q
1
Q
2
(a) Circuit
(b) Timing diagram
Figure 5.26. A modulo-6 counter with asynchronous reset.
T Q
Q
Clock
T Q
Q
T Q
Q
1
Q
0
Q
1
Q
2
(a) Circuit
Clock
Q
0
Q
1
Q
2
Count
(b) Timing diagram
0 1 2 3 4 5 0 1 2
Example 2
Which one is better? Synchronous reset or
Asynchronous reset and, Why?
Answer
The timing diagrams in Figures 5.25(b) and
5.26(b) suggest that synchronous reset is a
better choice than asynchronous reset
The flip-flops are cleared to 0 a short time
after the NAND gate has detected the count
of 5

Example 3
Answer
Example 4
Answer
Example 5
Answer
Answer (continued)
Other Types of Counter
BCD Counter
Binary-Coded-Decimal (BCD) Counter uses
decimal counting sequence
Ring Counter
Johnson Counter
Both (Ring & Johnson) counting sequence do
not represent binary numbers