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Introduction to Verification
Lecture 4
High-Level Modeling
Introduction to Verification
Outline
Introduction to Verification
Introduction to Verification
To avoid
latches
set all outputs of
combinatorial blocks
to default values at
the beginning of the
block
To avoid
internal buses
do not assign
registers from
two separate always
blocks
Introduction to Verification
Introduction to Verification
Introduction to Verification
end
RELEASE: begin
req <=1b0;
if (!ack)
begin
next_state <=
next_state <= state;
;
end
case(state)
endcase
end
MAKE_REQ: begin
always_ff @(posedge
req <= 1b1;
clk)
begin
if
if rst state <= ;
(ack)next_sate else state <=
<= RELEASE;
next_state;
end
always
begin
req <= 1;
wait (ack);
req <= 0;
wait
(!ack);
end
High-Level
Coding Style
Introduction to Verification
Coding Style
Synthesizable subset puts several constraints on your coding style
With no restrictions in high-level modeling, unmaintainable, fragile
and not portable code is easy to achieve
Must have discipline code will need to be modified
Assume an inexperienced audience
Introduction to Verification
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Introduction to Verification
TESTBENCHES
- structured according to
implementation needs
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Introduction to Verification
Encapsulation
internal coding can be changed
without affecting the communication,
so long as the new implementation
supports the same (or upwards
compatible) external communication
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Introduction to Verification
Encapsulation
Keep declarations as local as possible to avoid accidental interactions
with another portion of the code where the declaration is also visible
int i;
always
begin
for (i = 0; i < 32; i
= i + 1) begin
...
end
end
always
begin
for (i = 15; i >= 0;
i = i - 1) begin
...
end
end
always
begin
int i;
for (i
i + 1)
...
end
end
always
begin
int i;
for (i
i - 1)
...
end
end
= 0; i < 32; i =
begin
= 15; i >= 0; i =
begin
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Introduction to Verification
Encapsulation
SystemVerilog tasks and functions can contain local variables
task send(input [7:0] data);
reg parity;
...
endtask
function [31:0] average (input [31:0] val1,
input [31:0] val2);
reg [32:0] sum;
sum = val1 + val2;
average = sum / 2;
endfunction
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Introduction to Verification
Encapsulation
Local variables can be created while minimizing their scope and
potential undesirable interaction.
function bit eth_frame::compare(eth_frame to);
compare = 0;
...
if (this.data_len !== to.data_len) return;
begin
int i;
for (i = 0; i < this.data_len; i++) begin
if (this.data[i] !== to.data[i])
return;
end
end
...
compare = 1;
endfunction: compare
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Introduction to Verification
Encapsulation
The scope of variables used solely as for-loop iterators can be further
reduced by declaring them within the loop statement, often
eliminating the need for a begin/end block
function bit eth_frame::compare(eth_frame to);
compare = 0;
...
if (this.data_len !== to.data_len) return;
for (int i = 0; i < this.data_len; i++) begin
if (this.data[i] !== to.data[i])
return;
end
...
compare = 1;
endfunction: compare
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Introduction to Verification
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Introduction to Verification
drives and
samples low-level
signals according
to a predefined
protocol
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Introduction to Verification
Encapsulation
By default, SystemVerilog arguments are passed by value when the task is called
and when it returns. At no other time can a value flow into or out of a task via its
interface.
class arbiter;
...
// This task will not work...
task request(output logic
bus_rq,
input logic bus_gt);
// The new value does not
"flow" out
bus_rq <= 1b1;
// And changes do not "flow"
in
wait bus_gt == 1b1;
endtask: request
...
endclass: arbiter
class arbiter;
task request(ref output logic
bus_rq,
ref input logic bus_gt);
// The new value will "flow" out
bus_rq <= 1b1;
// And changes will "flow" in
wait bus_gt == 1b1;
endtask: request
endclass: arbiter
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Introduction to Verification
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Introduction to Verification
OOP: Class
A user-defined data type
A collection of variables and subprograms that create object types
Consists of:
o data members (class properties)
o tasks and functions to access the data (methods)
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Introduction to Verification
OOP: Class
What are objects?
o Objects are instances of a class
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Introduction to Verification
OOP: Class
Data Members
consume memory
each data member is local to
each object instance
can be global as well
Methods
do not consume memory
are global to the class
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Introduction to Verification
OOP: Class
A simple class declaration:
class C;
int x;
task set (int i);
x = i;
endtask
function int get;
return x;
endfunction
endclass
data member
methods
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Introduction to Verification
OOP: Class
An object must be created to use the class:
C c1;
c1 = new;
or
C c1 = new;
Having created a class object, we can use the class methods to assign and
look at the data value, x:
initial
begin
c1.set(3);
$display("c1.x is %d", c1.get());
end
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Introduction to Verification
OOP: Class
Not objects:
o Modules & interfaces
are hierarchical constructs, not data structures
cannot be assigned nor passed to tasks or functions as arguments
cannot be compared or used in expressions
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Introduction to Verification
OOP: Inheritance
What if there is a class that does almost everything you need, but it is
missing only that one little feature, what will you do?
Traditional approach:
Make a copy of the useful code, call it something else, and make
the necessary modifications.
But with inheritance:
Your needs can be built upon existing classes by only specifying
the desired difference in behavior.
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Introduction to Verification
OOP: Inheritance
parent or base class original class
derived class
o the new class inheriting from the base
o inherits the properties and methods of its parent or base class
o may add new properties and methods, or modify the inherited properties
and methods
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Introduction to Verification
OOP: Inheritance
Consider the example of the class Register:
class ShiftRegister extends Register;
task shiftleft; data = data << 1; endtask
task shiftright; data = data >> 1; endtask
endclass
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Introduction to Verification
OOP: Polymorphism
polymorphism means to have many forms
classes on different branches can be treated as if they were the same
class, when viewed as a common base class
the ability to request that the same operations be performed by a
wide range of different types of things
o you can ask many different objects to perform the same action
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Introduction to Verification
OOP: Polymorphism
Example: without virtual
class A ;
task disp ();
$display(" This is class A ");
endtask
endclass
class EA extends A ;
task disp ();
$display(" This is Extended class A ");
endtask
endclass
program main ;
EA my_ea;
A my_a;
initial
begin
my_a = new();
my_a.disp();
my_ea = new();
my_a = my_ea;
my_a.disp();
end
endprogram
RESULTS
This is class A
This is class A
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Introduction to Verification
OOP: Polymorphism
Example: with virtual
class A ;
virtual task disp ();
$display(" This is class A ");
endtask
endclass
class EA extends A ;
task disp ();
$display(" This is Extended class A ");
endtask
endclass
program main ;
EA my_ea;
A my_a;
initial
begin
my_a = new();
my_a.disp();
my_ea = new();
my_a = my_ea;
my_a.disp();
end
endprogram
RESULTS
This is class A
This is Extended class A
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Introduction to Verification
C++
Randomization, Constrainability,
Functional coverage measurement
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Introduction to Verification
Randomization
Constrainability
Functional coverage
measurement
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Introduction to Verification
Connectivity
Time
Concurrency
-
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Introduction to Verification
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Introduction to Verification
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Introduction to Verification
Module thread
intended to model the design
Program thread
intended to model the testbench
composed of:
- initial blocks, concurrent signal
assignments and forked threads
defined inside program blocks
- class methods instantiated in a
program block and invoked by a
program thread
include pass/fail action block in
properties.
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Introduction to Verification
Assign zero-delay
nonblocking values
1
Execute module
threads
Advance Time
Evaluate
assertions
3
If there is nothing left to be done at the current time,
there must be either:
1. A thread waiting for a specific amount of time
2. A nonblocking value to be assigned after a non-zero
delay
Execute program
threads
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Introduction to Verification
Summary