5.GB - SS42 - E2 - 1 ZXG10 IBSC Structure and Principle (1G) 118

ZXG10 iBSC Structure and Principles
Course Objectives
After learning this course, you will:
Understand the functions, features and specifications

of ZXG10 iBSC
Master the hardware structure of ZXG10 iBSC and the
working principles of its shelves and boards
Master the interface design and logical units of ZXG10
iBSC
Master signal streams on the control plane and the
user plane of ZXG10 iBSC
Master the internal cable connections of ZXG10 iBSC
Contents
iBSC System Overview

iBSC Hardware Structure
iBSC Board Principles
iBSC Interface Implementation and Logical Units
Signal Flow on iBSC Control Plane and User
Plane
iBSC Internal Cable connection
Network Structure
MSC/VLR
GMSC
Nc
BTS
PSTN
Mc
BSC
BTS
Inter-PLMN
Nb
Gb
Iur-g
MGW
GMGW
IuCs
NodeB
RNC
IuPs
NodeB
SGSN
GGSN
What does "i" stand for?

intelligent
integration
intelligent identification of wireless

access intelligent error
self-correction
integrates multi-interfaces
E1/STM-1/IP integrates multi
transmission supported
immensity
intensify
large capability
supports 3072 TRX and 15000 Erl
with only two racks
intensified design
supports FR/EFR/HR/AMR/WB-AMR,
innovative NetSpeed wireless
enhanced technology
IP
All-IP platform
supports IP bearer
ZXG10 iBSC Product Features
Based on V3 universal hardware platform

All IP hardware architecture
Large capacity and strong processing
capabilities
Modular design with good scalar
Separation of control streams from media
streams
Supporting Flex A and Flex Gb
Coding scheme: FR/HR/EFR/FR-ARM/HRAMR
Transmission interface: E1/T1/FE/STM-1
Easy and smooth upgrade
Flexible networking modes
High integration and low power consumption
Universal All IP Hardware Platform
GSM / WCDMA
TD-SCDMA
Universal
Hardware Platform
Totally 16 boards
All IP
CDMA 2000
NGN
Modularity
Smooth
Upgrade
Modular Design
Boards
Different software can be used to define

different functions for the same board.
AIU, BIU, PCU and TCU are logical units; All
interface units are in the resource shelf.
Easy Scalability
The system can be

expanded via adding
RCBUs.
3 RCBUs/2 racks.
BGSN
BGSN
BGSN
BCTC
BCTC
BGSN
BGSN
BGSN
BGSN
BPSN
BPSN
BGSN
RACK1
RACK1
RACK2
Multiple Access Modes and Smooth Evolution
iBSC supports multiple access modes
E1/T1
STM-1
FE/GE
Evolution
iBSC
Advantages
iBSC
iBSC
RNC
RNC&BSC
BSC
RNC
RNC&BSC
BSC
BSC
RNC&BSC
BSC
BSC
RNC&BSC
Saves 20% space when 2G and 3G

modules are integrated into the same
site.
Shares cabinets, spare parts,
transmission and OMM.
Saves power consumption
Saves engineering and network
upgrade cost
ZXG10 iBSC Interfaces
No.
Logical
Interface
Link Object
1.
MSC
2.
Gb
SGSN
3.
Abis
BTS
E1, STM-1, FE/GE
4.
Ater
iTC
STM-1, E1
Interface Type
STM-1, E1, FE/GE
E1, FE/GE
ZXG10 iBSC Interface Specifications

A-Interface
Abis
Interface
Cabinet
E1(T1) A
Number of
Carriers
A Single
Cabinet
1024
Dual Cabinets
3072
E1(T1) Abis
A Single
Cabinet
1024
Interface
Capacity
Abis:208 E1(T1)
A:188E1(T1)
Abis:624 E1(T1)
A:700E1(T1)
Abis:3 pairs of
STM-1
3072
Abis:9 pairs of
STM-1
1024
3072
1024
1024
Dual Cabinets
3072
IP Abis
Abis:1 pair of GE
A:252E1(T1)
Abis :2 pairs of
GE
1024
IPoE Abis
(EIPI+DTB)
IPoE Abis
(EIPI+SDTB2
)
1024
Dual Cabinets
3072
A Single
Cabinet
Dual Cabinets
Abis:160 E1(T1)
A:188E1(T1)
Abis:480 E1(T1)
A:700E1(T1)
\
\
\
A:4 pairs of STM-1

Abis:624 E1(T1)
A:11 pairs of STM-1
Abis:3 pairs of STM-1
1024
3072
1024
1024
3072
Abis:1 pairs of GE
A:4 pairs of STM-1
Abis:2 pairs of GE
3072
3072
1024
3072
Abis:160 E1(T1)
A:4 pairs of STM-1
Abis:480 E1(T1)
A:11 pairs of STM-1
A:4 pairs of STM-1

11 pairs of STM-1
Abis:208 E1(T1)
A:1 pair of GE
Abis:624 E1(T1)
A:2 pairs of GE

A:2 pairs of GE
2048
3072
A:11 pairs of STM-1

1024
Interface Capacity
A:1 pair of GE
A:11 pairs of STM-1
A:700E1(T1)
A Single
Cabinet
Abis:208 E1(T1)
A:4 pairs of STM-1
A:700E1(T1)
A Single
Cabinet
IP A
Number
Number of
of
Interface Capacity
Carriers
Carriers
A:188E1(T1)
STM_1 Abis
Dual Cabinets
STM-1 A
Abis:1 pair of GE
A:1 pair of GE
Abis:2 pairs of GE
A:2 pairs of GE
1024
3072
1024
3072
Abis:160 E1(T1)
A:1 pair of GE
Abis:480 E1(T1)
A:2 pairs of GE
A:1 pair of GE
A:2 pairs of GE
ZXG10 iBSC Physical Specifications

Item
Specification
Dimensions (H*D*W) (mm)
2,000 * 800 * 600
Weight
<270Kg(1 rack)
<540Kg(2 rack)
Power Consumption
All E1:
2,558W per rack, 6,368W/2
racks
All IP:
2,542W per rack, 3,808W/2
racks
Power Source Requirements
-48V DC (-40V DC to -57V DC)
Operating Temperature
Long-term temperature: 0C
40C.
Short-term temperature: 5C45C.
Operating Humidity:
Long-term humidity: 2090%.

Short-term humidity: 5%
95%.
ZXG10 iBSC Performance Specifications

Item
Specification
BHCA
4,200K
Maximum traffic
15000 Erl
Maximum throughput over Gb

interface
E1 Gb: 256Mbps
IP Gb: 600Mbps
Maximum TRXs supported
One Rack: 1,024

Two Rack: 3,072
The all-IP architecture conforms to the trend towards an IPbased network
Large capacity and strong processing capabilities
Supports E1, T1, STM-1 and IP interfaces and flexible

networking modes
Contents

Plane
Hardware Architecture Introduction
Work Planes
Major Interfaces
Abis IP over E1, E1, IP

A TDM (E1, STM-1), IP
Gb TDM (E1), IP
(Ater)
Levels of Shelves
Control Plane & User Plane
Shelf Types
Control shelf (BCTC), resource shelf (BGSN), switch shelf

(BPSN)
Boards
ZXG10 iBSC Shelves

Control Shelf (BCTC)
System
(BGSN)
Resource Shelf
Clock
control and management
capture and distribution
Processing
(BCTC)
Control Shelf
System
of control plane signaling
operation and maintenance
Resource Shelf (BGSN)

(BGSN)
Resource Shelf
System
external access
Processing
(BPSN)
Switch Shelf
of universal services
Switch Shelf (BPSN)

Large-capacity
IP switch platform on the user plane
ZXG10 iBSC Boards

Shelf
Board
UIMC
Full Name
Universal Interface Module for
Control plane
BGSN
Level 2 switch of control plane signaling
Control and management of CS and PS services, processing of

BSSAP and BSSGP protocols, and resource management of the
system
Switch and convergence of control plane signaling
CMP
Control Main Processor
CHUB
Control HUB
OMP
Operation Main Processor
Operation and maintenance, system control, management and

monitoring
SBCX
X86 Single Board Computer
O&M server
CLKG
Clock Generation
Clock generation and distribution
ICM
Integrated Clock Module
Clock generation and distribution (with GPS)
GLI
Gigabit Line Interface
Level 1 switch, interface with the resource shelf
PSN
Packet Switch Network
SPB2
Signaling Processing Board
GUIM
Giga bit User Interface Module
GUP2
GSM Universal Processing
Processing of user plane protocols, such as TC, PCU and RTP
DTB
Digital Trunk Board
Provides 32 E1/T1 trunk interfaces
SDTB2
Sonet Digital Trunk Board 2
Provides two STM-1 interfaces
GIPI
GE IP Interface
Provides four FE interfaces or one GE interfaces for Abis/A/Gb
EIPI
E1 IP Interface
provides E1 or T1 based IP connection
BCTC
BPSN
Functions
Provides bi-directional user plane data switch with a capacity of 40

Gbps on each direction
Signaling processing, interface board (16 E1 lines for A/Gb,
eight E1 lines for Abis)
Level 2 switch between the control plane and the user plane,
resource shelf management
Physical and Logical Boards of ZXG10 iBSC

Physical
Board
GIPI
GUP2
SPB2
Logical Board
Functions
IPBB
Completes IP access over the Abis interface, and sever the control
plane from the user plane
IPI
Completes IP access over the A interface, and sever the control

plane from the user plane (signaling from service)
IPGB
Completes IP access over the Gb interface, and sever the control

plane from the user plane
BIPB2
Search 20 ms TRU frames according to the channels and form IP

packets
For IP access over the Abis interface, it also processes RTP.
AIPB
It processes RTP and forms IP packets
UPPB2
User plane protocol processing in the PS field
DRTB2
Completes the transcoding and rate adaptation of TRAU frames, and

provides FR, EFR, AMR and TFO functions
LAPD2
LAPD signaling processing
SPB2
MTP2 protocol processing
GIPB2
Provides Gb interface functions, and processes the FR, NS and

partial BSSGP of GPRS.
Introduction to BCTC
Control Shelf
1
Rear Board
R
S
V
B
10 11 12 13 14 15 16 17
R R
U U
I
I
M M
2 3
R
S
V
B
R
M
P
B
R
M
P
B
R R
C C
K K
G G
1 2
R
C
H
B
1
R
C
H
B
2
BCTC
1
Front Board
Completes the global operation

and maintenance of the
system, provides the global
system clock, manages the
control plane, and responsible
for the switch between the
control plane and the Ethernet
Each iBSC must be configured
with one control shelf, which is
located in Shelf 2 in Rack 1
C C
M M
P P
C
M
P
C
M
P
6
S
B
C
X
8
S
B
C
X
10 11 12 13 14 15 16 17
U U
I
I
M M
C C
O
M
P
O
M
P
I
I
C C
M M
C
H
U
B
C
H
U
B
No.
Board Name
Number
Slot No.
Backup
OMP
1112
1+1
CMP
2~4
1~4
1+1
CHUB
15~16
1+1
ICM
13~14
1+1
UIMC
9~10
1+1
SBCX
57
1+1
BCTC Working Principles
The clock generation board

(ICM) distributes clock signals to
the switch shelf and resource
shelves through cables.
OMP and SBCX boards are
connected to the iOMCR
through the hub to sever intranet
segments from Internet
segments.
The CHUB acts as the control
stream convergence center for
the control streams from the
switch shelf, the resource shelf
and the control shelf.
BPSN
BGSN
GUIM
UIMC
8K/16M
CHUB
UIMC
ICM
Ethernet
CMP
OMP
SBCX
BCTC
HUB
HUB
Outside
network
Introduction to BGSN
R
S
P
B
R
D
T
B
R
S
P
B
10 11 12 13 14 15 16 17
R
G
U
M
1
R
G
U
M
2
R
D
T
B
R
S
P
B
BGSN
1
Front Board
Rear Board
Provides system external

interfaces.
Processes universal services.
Acts as the Level 2 switch
center.
The BGSN is configured in
Shelf 1 and Shelf 3 of the
main rack. When a single
shelf constitutes an office, it is
configured in Shelf 2.
Gigabit Resource Shelf
10 11 12 13 14 15 16 17
G
U
P
2
S
P
B
2
D
T
B
S
P
B
2
G
U
P
2
G G
U U
I
I
M M
D
T
B
E
I
P
I
G
U
P
2
S
P
B
2
No.
Board Name
Number
Slot No.
Backup
1
2
3
4
5
6
7
GUIM
GIPI
GUP2
DTB
SDTB2
SPB2
EIPI
2
0-8
-
9~10
1-8,11-17
2-8,11-16
1-8,11-14,17
1-8,11-16
1-8,11-17
1-8,11-17
1+1
1+1
1+1
-
BGSN Working Principles
The GUIM board is the

convergence and switch center for
various data in the resource shelf. It
completes the information exchange
between modules.
The GUIM board interconnects with
the GLI board in the packet switch
shelf to carry out level 1 switch
between different resource shelves.
DTBs and SPBs provide E1
interfaces, and SDTBs provide
STM-1 access.
GIPI boards provide FE and GE
access.
Processes universal services
(conversion from TC and TDM to IP
packets, processing of user plane
protocols).
BPSN
BCTC
GLI
CHUB
ICM
GUP2
GUIM
BGSN
GUP2
SDTB 2
STM-1
DTB
E1
SPB2
E1
GIPI
FE
GE
Introduction to BPSN
Packet Switching Shelf

1
10 11 12 13 14 15 16 17
Rear Board
R
U
I
M
2
R
U
I
M
3
BPSN
Front Board
Interconnects BGSNs and

Level 1 switch centers on the
user plane.
Each iBSC should have one
BPSN, which is configured in
Shelf 4.
If the iBSC has two BGSNs,
then the BPSN is not
mandatory. However, this can
affect the capacity expansion
of the system.
G
L
I
G
L
I
G
L
I
G G
L L
I
I
G
L
I
P
S
N
P
S
N
10 11 12 13 14 15 16 17
C C
M M
P P
C C
M M
P P
U
I
M
C
U
I
M
C
No.
Board Name
Number
Slot No.
Backup
PSN
7~8
Load sharing
GLI
2~6
1~6
Load sharing
CMP
0~2
11~14
1+1
UIMC
15~16
1+1
BPSN Working Principles
The GLI board receives user

plane data from the GUIM
board.
The PSN provides 40Gbps
data switch capacity.
The UIMC receives clock
and control signals from the
control shelf and distributes
control & management
interfaces and clock signals
in the shelf.
BPSN
PSN
BCTC
FE
UIMC
CHUB
GLI
ICM
LVDS
GLI
......
fiber
GUIM
GUIM
BGSN
BGSN
Shelf Configuration (1)

PWRD
1
PWRD
10 11 12 13 14 15 16 17
BIU
AIU
S
P
B
2
G
U
P
2
D
T
B
D D
T T
B B
C
M
P
C C C
M M M
P P P
G
U
P
2
D
T
B
D
T
B
S
G
P
I
B
P
2
I
/
G
U
I
M
G
U
I
M
U
I
M
C
U O
I
M M
C P
S
G D
P
I T
B
P
2
B
I
/
D G
T U
B P
2
S
P
B
2
C
H
U
B
C
H
U
B
S
P
B
2
R
S
P
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
TCU
S
B
C
X
O
M
P
I
C
M
I
C
M
R
S
V
B
R
S
V
B
R R R
U U M
I
I P
M M
2 3 B
G G D
U U
P P T
2 2 B
G
L
I
G
L
I
G
L
I
D
T
B
G G
L L
I I
G
U
P
2
D
T
B
D
T
B
G P
L S
I N
P
S
N
G G
U U
I
I
M M
D
T
B
G D
U
T
P
B
2
C
M
P
C
M
P
D
T
B
G
U
P
2
G S
U P
P B
2 2
R
D
T
B
R
S
P
B
R
D
T
B
R
D
T
B
R
D
T
B
G
U
P
2
D G
U
T P
B 2
D
T
B
D D
T T
B B
G D
U
P T
2 B
D
T
B
G D
U
P T
2 B
D G
U
T P
B 2
R
C
K
G
2
R
D
T
B
R
D
T
B
R
C
H
B
1
R
C
H
B
2
Abis Interface E1
R R
G G
U U
M M
1 2
R
D
T
B
R
S
P
B
10 11 12 13 14 15 16 17
FAN
D
T
B
G
U
I
M
G
U D
I T
M B
S
P
B
2
S
P
B
2
S
P
B
2
G D
U
P T
2 B
D
T
B
G
U
I
M
G
U
I
M
D
T
B
G D
U
P T
2 B
D
T
B
G
U
P
2
G
U
P
2
S
P
B
2
R
S
P
B
G D
U
P T
2 B
R
D
T
B
G S
U P
P B
2 2
R
S
P
B
G D
U
P T
2 B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
FAN
S
P
B
2
R
C
K
G
1
R
S
P
B
PWRD
10 11 12 13 14 15 16 17
D
T
B
G
U
P
2
R
M
P
B
R
S
P
B
FAN
FAN
S
P
B
2
R
D
T
B
R R
U U
I
I
M M
2 3
PWRD
2
R
D
T
B
U U
I
I
M M
C C
FAN
R
R
S
G
P
E
B
R
/
FAN
FAN
S
P
B
2
10 11 12 13 14 15 16 17
R R R
R G G SR
D U U PG
T M M BE
B 1 2 /R
PCU
S
B
C
X
9
FAN
FAN
D
T
B
D
T
B
G
U
P
2
D
T
B
D
T
B
G G
U U
I
I
M M
D
T
B
S
P
B
2
G D
U
P T
2 B
D
T
B
G D
U
P T
2 B
D
T
B
G
U
I
M
G
U
I
M
D
T
B
G D
U
P T
2 B
FAN
S
P
B
2
D
T
B
G
U
P
2
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
R G
D U
T
M
B 1
R
R R G
D D U
T T M
B B 1
FAN
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
G
U
M
2
R
G
U
M
2
R R
G G
U U
M M
1 2
R R
G G
U U
M M
1 2
FAN
R
S
P
B
R
S
P
B
R
S
P
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R R
S S
P P
B B
R
D
T
B
R
D
T
B
R
D
T
B
R
S
P
B
R
S
P
B
R
D
T
B
R
D
T
B
A-Interface E1
Cabinet Configuration (2)

PWRD
1
PWRD
10 11 12 13 14 15 16 17
BIU
AIU
PCU
G
U
P
2
G
U
P
2
G
I
P
I
G
I
P
I
C
M
P
C C C
M M M
P P P
G
U
P
2
G
U
P
2
G
I
P
I
U U O O I
I
I
M M M M C
C C P P M
S
B
C
X
S
B
C
X
TCU
G G
U U
I
I
M M
G
U
P
2
G
I
P
I
G
U
P
2
G
U
P
2
G
I
P
I
G
U
P
2
G
L
I
G
L
I
G
L
I
G
I
P
I
G
I
P
I
G
L
P
S
N
C
H
U
B
C
H
U
B
C
M
R
S
V
B
R R R
U U M
I
I P
M M
2 3 B
R
S
V
B
G G G
U U U
P I
I
2 M M
G G
U U
P P
2 2
P
S
N
C C
M M
P P
G
I
P
I
G
I
P
I
G
U
P
2
G
U
P
2
R
G
E
R
R
G
E
R
R
G
E
R
R R
G G
U U
M M
1 2
R
G
E
R
G
I
P
I
G
U
P
2
G
U
P
2
G
U
P
2
R
C
K
G
1
R
C
K
G
2
R
C
H
B
1
R
C
H
B
2
Abis Interface IP
PWRD
10 11 12 13 14 15 16 17
G G
U U
I
I
M M
FAN
FAN
R R
G G
E E
R R
FAN
10 11 12 13 14 15 16 17
FAN
FAN
G
I
P
I
R
M
I
N
C
R R
U U
I
I
M M
2 3
U U
I
I
M M
C C
PWRD
2
R
M
P
B
R
M
I
N
C
FAN
FAN
10 11 12 13 14 15 16 17
R R
G G
U U
M M
1 2
R R
G G
E E
R R
FAN
G
I
P
I
9
FAN
FAN
G
U
P
2
G
U
P
2
R
G
E
R
R
G
E
R
R R
G G
U U
M M
1 2
FAN
FAN
A-Interface IP
Cabinet Configuration (3)

PWRD
1
PWRD
10 11 12 13 14 15 16 17
E
I
BIU P
I
AIU
PCU
D
T
B
D E
T I
B P
I
C
M
P
C C C
M M M
P P P
G
I
P
I
G
I
P
I
TCU
D
T
B
D
T
B
G G SG S G
U U PI PI
B B
I
P P
I
2 2
M M I I
/
/
G D
U T
P B
2
U U O
I
I
M M M
C C P
S
B
C
X
S
B
C
X
G G
U U
P P
2 2
G G
U U
P P
2 2
O
M
P
S
P
B
2
G
U
P
2
G
U
P
2
G
U
P
2
I
I C
H
C C U
M M
B
C
H
U
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
S
V
B
R R R
R G G SR
D U U PG
T M M BE
B 1 2 / R
R
SR
G
P
E
B
R
/
R
S
P
B
R R R
U U M
I
I P
M M
2 3 B
R
M
P
B
R
C
K
G
1
R
S
V
B
G
L
I
G
L
I
G
L
I
G G
L L
I I
G P
L S
I N
G G G G
U U I I
I
I P P
M M I I
P
S
N
C
M
P
G G
U U
P P
2 2
C
M
P
R
C
H
B
2
R R
U U
I
I
M M
2 3
U U
I
I
M M
C C
FAN
PWRD
2
R
C
H
B
1
R R R R
G G G G
U U E E
M M R
R
1 2
R R R R
G G G G
E E E E
R R R R
G
U
P
2
FAN
R
C
K
G
2
Abis Interface IPoE
FAN
FAN
G G
I I
P P
I I
10 11 12 13 14 15 16 17
FAN
FAN
PWRD
10 11 12 13 14 15 16 17
10 11 12 13 14 15 16 17
FAN
FAN
E
I
P
I
D
T
B
D E
T I
B P
I
D
T
B
D
T
B
G D
U T
P B
2
G G
S
U U P
I
I B
M M 2
E
I
P
I
D
T
B
D E
T I
B P
I
D
T
B
D
T
B
G D
U T
P B
2
G
U
I
M
G
U
I
M
FAN
FAN
S
P
B
2
S
P
B
2
S
P
B
2
G
U
P
2
G
U
P
2
G
U
P
2
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
S
P
B
2
G G
U U
P P
2 2
G
U
P
2
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R
D
T
B
R R
G G
U U
M M
1 2
R
G
U
M
1
FAN
R
G
U
M
2
FAN
R
S
P
B
R
S
P
B
R
S
P
B
R R
S S
P P
B B
A-Interface IP
Contents

Plane
OMP
The OMP board processes the global procedure,

performs O&M related control of the entire system
(including O&M proxy), and connects to the OMM
through the 100M Ethernet.
As the processing core of iBSC operation &
maintenance, the OMP board can directly or indirect
monitor and manage all boards in the system. It
provides two links (Ethernet interface and RS485) for
configuration management of system boards.
OMP
CPU A is responsible for global operation & maintenance.

CPU B is the Router Processing Unit (RPU).
The HD Disk is a 2G hard disk to store system data, for example,
board software version files, configuration files and logs.
CPU B
RS485,RS232
RS232
DEBUG 2-232
RS485
CP FE
CPU Core
Back Board
What are the

functions of the
RPU?
Logic Unit
Ethernet
Power
Management
RS485,RS232
RS232
CPU Core
1. Enables intranet addresses within the

BSC to communicate with each other.
2. Provides routes for the operation and
maintenance of the BTS.
HD Disk
CP FE
CPU A
OMC2
RS485
GPS485
PD 485
RS232
DEBUG1- 232
OMC1
Ethernet
CMP
The CMP board controls and manages service

calls in the PS and CS fields, and manages the
resources of BSSAP, BSSGP and the system.
Its physical board is MPx86/2, the same as the
OMP, but the memory capacity is slightly different:
1GB/CPU for the OMP, and 2GB/CPU for the
CMP, and the OMP has a hard disk).
UIMC
The UIMC is responsible for Ethernet Level 2 switch

within the BCTC and the BPSN and the management of
the BCTC.
The UIMC provides the clock drive function inside the
BCTC and the BPSN. It inputs 8K and 16M signals, which
are sent to different slots in the BGSN after phase lockup
to provide 16M and 8K clocks for the boards.
The UIMC provides management interfaces for the BCTC
and the BPSN; it also provides board resetting and
resetting signal collection functions for the BCTC and the
BPSN.
UIMC
The UIMC provides one internal GE interface that is connected to the
CHUB.
RS485
Inner Bus
DEBUG 232
Logic Unit
Back Board
Clock Unit
CPU
DEBUG FE
Inner Bus
CLKIN
CP FE, CP GE
User Plane
Switch
Ethernet
Switch Unit
Control Plane
Switch
CP FE 1~10
CHUB
The CHUB works together with the UIMC/GUIM to be

responsible for control plane data stream exchange and
convergence in the system.
The control plane data from each shelf is sent to the
Ethernet switching unit of CHUB board through the
Ethernet cables on the control plane.
The data is then sent to UIMC board of the BCTC
through GE for level-2 switch, and then distributed to
each CMP board for processing.
CHUB
The RCHB1 board has three FE buses, on which FE interfaces are grouped as
FE18, FE916 and FE1724.
The RCHB2 board has three FE buses, on which FE interfaces are grouped as
FE2532, FE3340 and FE4146.
Logic Unit
CPU
DEBUG FE/232
Back Board
Inner Bus
CP GE
Ethernet
Switch
Ethernet
Switch
Ethernet
Switch Unit
FE1 FE1
FE1
FEn
ICM
Responsible for system clock supply and external

synchronization. The board extracts clock reference via
the A interface and drives multiple channels of clock
reference signals for use by each interface unit.
It receives GPS satellite signals and extract 1PPS signals
and related TOD messages. The 1PPS signals are used
as reference for phase lockup in order to create
PP2S,19.6608MHz and 8 K clock references for iBSC.
Supports background or manual selection of clock
references, including BITS, line (8 K), GPS, local (Level 2
or Level 3); supports software shielding of manual
switchover.
Supports four work modes: CATCH, TRACE, HOLD and
FREE.
ICM
8 K reference inputwhen DTB/SDTB2 provides the clock reference, it

connects with the 8KOUT/DEBUG-232 interface of RGIM1.When SPB2
provides the clock reference, it connects with the 8KOUT/CPU1-RS232
interface of RSPB.
One CLKOUT interfaces outputs a one-to-six cable; one shelf has two
UIM/GUIM boards with two clock sockets, so one CLKOUT interface can
connect with three shelves. The RCKG1 board has two CLKOUT interfaces
providing six clock output lines, that is , it can connect with six shelves.
GPS
8KIN
2Mbps/2MHz
Reference
Selection Unit
GPS Unit
PP2S/16CHIP
PLL Unit
8K ,16M , 32M , 64M

CLKOUT
Oscillastor
CPU
RS232
RS485
Inner Bus
SBCX
The SBCX board is the server board. It mounts the server

on the rack.
It provides the keyboard, the mouse and the VGA
interface.
Uses Sossaman dual-path dual-core CPU with a
frequency of 2G Hz.
Supports multiple operating systems, including Windows
XP/2000/2003, Linux and Solaris.
Provides three FE interfaces, two GE interfaces and one
RS232 serial port.
Provides four universal USB interfaces.
Supports boot from hard disk and boot from USB drive.
SBCX
OMC1(eth3) is set to an external network address to communicate with

NetNumen M31 server.
OMP1(eth6) is set to an intranet address to communicate with the
OMP.
VGA
CPU
Dual Core
Outside
Interface
USB
Mouse(MS)
KeyBoard(KB)
OMC1
OMC2
Outside
Interface
OMP1
RS232
USB
SAS
Controller
SAS HD1
SAS HD2
DTB
Provides 32 E1/T1 links for external connections.

Supports extraction of 8K synchronization clock from the
lines, which is transferred to the CLKG/ICM board through
the cable as clock reference.
Supports 120/75 impedance selection for E1 cables,
and supports coaxial cables and twisted-pair cables.
Supports 100 twisted-pair T1 cables.
DTB
8KOUT/DEBUG-232
CP FE RS232RS 485
CPU
Clock
Back Board
Clock Unit
Logic Unit
E1/T1 1~32
Interface Unit
Circuit Switch
Unit
HW
DTP DIP Switches
S1
ON
S2
ON
S3
ON
S4
ON
S5
ON
S7
S8
S10
S11
ON
ON
ON
ON
S6
ON
S9
ON
S12
ON
X23
DTP DIP Switches

DIP
Switch
Purpose
S1~S6
S9
S12
Used to set the

resistances that
match the
impedances of
different E1 paths to
75 or 120 .
S7
S8
Used for indicating

the receiving
matching
impedance of
corresponding E1
chip to the CPU.
S10
S11
Used for reporting

the long/short wire
status of each E1
chip to the CPU.
Switch Configuration
Default Location
Mode
75
ON
ON
ON
ON
120
OFF
OFF
OFF
OFF
75
ON
ON
ON
ON
120
OFF
OFF
OFF
OFF
SHORT
HAUL
ON
ON
ON
ON
LONG
HAUL
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
RDTP Jumpers
On the RDTB, the E1 cable

works in the 75 unbalanced
coaxial transmission mode by
default.
If the E1 line uses 120
balanced transmission mode,
the short-circuit block at X9
X16 on the RDTB needs to be
removed.
The sending end is grounded
through the jumper. The
receiving end is connected to
a capacitor and then grounded
through the jumper. Jumpers
X9X16 are used to complete
such settings.
RDTP Jumpers
X9-X16 Pin Connection
Definitions
1-2
Connect E1_TXN-R to the protection ground (Path N)
3-4
Connect E1_RXN-R to the protection ground (Path N)
5-6
Connect E1_TXN+1-R to the protection ground (Path

N+1)
7-8
Connect E1_RXN+1-R to the protection ground (Path

N+1)
9-10

N+2)
11-12

N+2)
13-14

N+3)
15-16

N+3)
SDTB2
The SDTB2 acts as the digital trunk interface board. It

provides two 155M STM-1 standard interfaces.
Supports CAS and CCS, and provides an access
processing capacity equal to 126 E1 lines or 168 T1 lines.
Outputs one path of differential 8 K synchronous clock
signals for the reference of the clock board
SDTB2
8KOUT/DEBUG-232
CP FE RS232RS 485
CPU
Clock
Back Board
Clock Unit
Logic Unit
STM-1
STM-1
Interface Unit
Circuit Switch
Unit
HW
SPB2
According to its functions, the SPB2 board can be classified into the
LAPD processing board (LAPD2), the signaling processing board
(SPB2) and the Gb interface processing board (GIPB2).
The LAPD2 board processes LAPD signaling. LAPD signaling data
from the BTS are received by the DTB/SPB/SPB2 board, and then
switched to the LAPD2 board through the circuit switching net on the
UIM board in the local resource shelf or the GUIM board in the local
Gigabit resource shelf. The LAPD2 completes the processing of
LAPD signaling data.
The SPB2 board processes MTP2 and X.25 protocols. It supports
extraction of 8 K synchronization clock from the lines, which is
transferred to the CLKG board through the cable as clock reference.
The GIPB2 board processes the FR, NS and partial BSSGP protocols
for the GPRS, and provides Gb interfaces.
SPB2
CPU4-RS232
CPU3-RS232
CPU2-RS232
CPU 4
CP FE
CPU 3
Ethernet
Switch Unit
UP FE
CPU 2
8KOUT/CPU1-RS232
RS232RS 485
Clock Unit
Clock
Logic Unit
E1/T1 1~16
Interface Unit
Circuit Switch
Unit
HW
Back Board
CPU 1
SPB2
Interface unit, which connects with the switching unit and

provides E1 interfaces.
Circuit switch unit, which implements the switching
between interface unit circuits and backplane circuits.
CPU, which implements signaling processing, board
management and internal connection control.
Ethernet Switch Unit, which implements control plane and
user plane data switch and provides FE interfaces.
Clock Unit, which extracts line clock signals and sends
them to the ICM board.
Each SPB2 board contains four CPUs.

Each SPBs board provides 16 E1/T1 interfaces.
GIPI
The GIPI board provides IP interfaces between iBSC and

the BTS, the SGSN and the MSC/MGW.
Implements Layer 3 protocol interface processing,
separates control plane data from user plane data, and
sends the data respectively to the Ethernet interfaces on
the internal control plane and user plane.
According to functions, GIPI can be classified into four
functional boards:
Abis interface Gigabit IP interface board(IPBB)
A interface Gigabit IP interface board IPAB(Signaling)
A interface Gigabit IP interface board IPI signaling and service
Gb interface Gigabit IP interface board(IPGB)
GIPI
The Interface Unit receives data and sends it to the service processing unit,
which separates user plane data from control plane data. User plane data is
then sent to the GUP2 through the user plane switch network, and control
plane data is sent to the CMP through the control plane switch network.
The GIPI board can choose RGER (providing one GE interface) or RMINIC
(providing four FE interfaces) as its rear board.
Processing Unit
GE1
GE2
Back Board
RS232
DEBUG1-232
CPU
Logic Unit
CP FE, UP GE
Interface
Unit
DEBUG2-232
EIPI
The EIPI board provides E1 or T1 based IP connection and

works together with the DTB. It has no external interface
and no rear board. One EIPI works together with two DTBs
to provide up to 64 E1 or T1 ports.
EIPI
The interface unit receives HW data and sends it to the HPS daughter
card. The data is then processed according to the HDLC protocol and
then sent to the service processing unit. It sends user plane data
through the user plane switch network to the GUP2 for processing, and
sends control plane data through the control plane switch network to
the CMP for processing.
HW
HPS Subcard
Processing Unit
Back Board
Interface
Unit
RS232
CPU
Logic Unit
CP FE, UP GE, HW
GUIM
The GUIM performs Ethernet Level 2 switching between the control

plane and the user plane in the Gigabit resource shelf, the CS field
timeslot multiplexing slot switching and Gigabit resource shelf
management. It also provides external interfaces for the Gigabit
resource shelf.
It has the capability of 16 K circuit switching, and provides an internal
circuit switching network for the GE resource shelf.
It provides the clock drive in the resource shelf. It inputsPP2S, 8K
and 16M signals, which are sent to different slots in the resource
shelf after phase lockup to provide 16M, 8 K and PP2S clocks for
resource modules in this shelf.
The UGIM board performs Gigabit resource shelf management and
provides RS485 management interfaces in the Gigabit resource shelf;
It also provides board resetting and in-slot signal collection functions.
GUIM
Circuit
Switch Unit
HW
RS485
Inner Bus
DEBUG 232
Clock Unit
CPU
CP FE
Inner Bus
Ethernet
Switch Unit
CLKIN
4*1 Gbps optical for UP
UP GE
Back Board
Logic Unit
CP FE 1~6
User Plane
Switch
Control Plane
Switch
GUP2
According to functions, GUP2 boards are classified into five functional

boards: Abis interface processing board BIPB2, A interface
processing board AIPB, user plane processing board UPPB2, dual
rate transfer board DRTB2 and Ater interface processing board TIPB2.
Over the STM-1 or E1 Abis interface, CS and PS services from the BTS
are switched to the BIPB2 board through the UIM board in the local
resource shelf or the GUIM board in the local Gigabit resource shelf. The
BIPB2 board searches 20ms TRU frames or PCU frames and form them
into IP packets, which are sent to the TCU or the UPU for processing.
Over the IP Abis interface, the BIPB2 board is also used to process RTP.
The DRTB2 implements code conversion, finishes TRAU frame conversion
and rate adaptation, and provides FR/EFR/HR/AMR/TFO function.
The AIPB board processes RTP and forms data into IP packets over the A
interface.
The UPPB2 processes user plane protocols such as BSSGP, PDCP and
GTP_U under the A/Gb mode.
GUP2
Each GUP2 board has 15 DSPs.
HW
Circuit Switch
Unit
Logic Unit
Clock Unit
Ethernet
Switch Unit
UP GE
DSP Unit
CPU
DSP
P
DSP
P
CP FE
Back Board
GUP2
CPU: responsible for board management, and provides

control plane FE interfaces for external connection.
DSP: processes universal services, including functions of
BIPB2, AIPB, DRTB2, UPPB2 and TIPB2.
Circuit Switch Unit: connects the serial ports of multiplechip DSP with the circuit switching network.
Ethernet Switch Unit: implements the Ethernet
connections for multiple-chip DSP and provides the user
plane FE interface for external devices.
Clock Unit: provides necessary clock signals for the units
on the board.
GLI
The GB Line Interface (GLI) board is located at level 1

switching subsystem of iBSC. It finishes physical layer
adaptation, IP package query, segmentation, forwarding,
and flow management functions, processes bi-directional
2.5Gbps forwarding, and implements the interfaces to
different resource shelves and external interface
functions.
GLI
Interface Unit: provides GE optical interface and supports physical

backup. SD1SD2, SD3SD4, SD5SD6 and SD7SD8 are backup
groups.
Processing Unit: implements bi-directional IP packet table look-up,
fragmenting, forwarding and traffic management.
Queue Management Unit: implements bi-directional queue
management.
The GE optical interface receives user plane data from the GUIM and
sends it through the backplane to the PSN board for user plane data
exchange.
SD1~SD8 (GE Optical)
Optical&Ethernet
Interface Unit
Processing Unit
Queue Management
Unit
Logic Unit
CPU
Back Board
CP FE
PSN
Inner bus
CPU
CP FE
Back Board
Provides bi-directional
user plane data switch
with a capacity of 40
Gbps on each direction
The data from each GLI
board is sent to the Matrix
Switching Unit through
the high-speed serial
links on the backplane. It
is switched and then sent
to the destination GLI
board.
LVDS
Logic Unit
Matrix Switch Unit
Peripheral Monitor Unit (PMU)
Includes the PWRD board and the alarm box

PWRD is responsible for collecting some peripheral and
environment board information within the cabinet,
including the power distributor and fan status as well as
some environment alarms like temperature/humidity,
smog, water and infrared alarms. Each cabinet has one
PWRD board.
The Alarm Box (ALB) can report system alarms at
different levels according to system fault grades to
facilitate timely interference and handling by equipment
management personnel.
Board Summary 1
Board Summary 2
Board Summary 3
Control Plane and User Plane Interconnection

BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
BGSN
GUIM
UIMU( UIM_2)
User Control
Circuit
plane
plane
GUP2
HUB
SPB2
DTB
SDTB2
E1
Abis/A /Gb
STM-1
GUIM
UIMU( UIM_2)
User
Control
Circuit
plane
plane
GUP2
GIPI
IP
iOMCR Client
Active/Standby Board Design
Key boards have 1+1 backup.

Key interface boards such as GIPI and SDTB can have 1+1
backup if necessary.
GLI and PSN boards work in the load sharing mode.
BGSN
BCTC
OMP/CMP
(Standby)
GUIM (Main)
OMP/CMP
(Main)
Control Plane
CHUB
User Plane
UIMC
CHUB
GUIM (Standby)
Control Plane
User Plane
UIMC
BPSN
GLI/PSN
GLI/PSN
UIMC
UIMC
General Description of Boards
Front board and rear board
Rear boards are passive boards that provides cabling

from the backplane (such as E1 and network cables) in
order to work together with corresponding front boards.
Front boards are physical boards that process
resources. All system optical cables are led from the
front board panels.
All front boards have four indicators on their

panels (RUN, ENUM, ACT, ALM) to indicate board
status.
Indicators on Board Panels

Indicator
RUN
ALM
Color
Meaning
Green
Running
indicator
Red
Alarm
indicator
Description
Flashing at 1 Hz: the board is running normally
Flashing at 5 Hz: version downloading is in process.
Flashing at 5 Hz: version download fails; board self test
fails because of inconsistency between board and
configuration
Solid on: the microswitch is opened; the board is not in
position; or version files are not downloaded.
ENUM
Yellow
Board
extraction
indicator
Flashing at 5 Hz (quickly): the microswitch generates an

alarm because it is opened when the board is still running.
Flashing at 1 Hz (slowly): the board can be extracted. The
microswitch is opened when the board is running, and the
board is in standby mode or release the resource.
Solid off: the microswitch is normal.
ACT
Green
Active/stan
dby status
indicator
On: the board is active.
Off: the board is standby.
Contents

iBSC Interface Implementation and Logical
Units
Plane
iBSC Logical View

ZXG10 iBSC
CMPU
UPU
Access
Switch
TC Unit
BTS
Unit
Unit
O& M Unit
MSC
PMU
Pow er a nd Fa ns
SGSN
iBSC External Physical Interfaces

FE
E1
SGSN
MSC/ MGW
A
STM -- 1
Gb
DTB /SDTB2/GIPI
SPB2/GIPI
iBSC
DTB /SDTB2/GIPI
Abis
DTB /SDTB2
SBCX
GIPI
Ater
BTS
iTC
NetNumen
OMCB
MR
Access UnitAbis Interface Unit (BIU)
E1 Abis
IP Abis
E1 borne TDM link
FE/GE borne IP link
IPoE Abis
E1 borne IP link
BIU - E1 Abis
The interface board can be the DTB or SDTB2 board. The access
capacity of SDTB2 is four times that of the DTB.
E 1 Abis
to TCU or UPU
BIPB2
BIU
GUP2
DTB
to CMP
SPB2
32
GUIM
1
2
User Plane
Switching
Network
Control Plane Switching Network
LAPD2
E1/ T1
Internal
Ethernet
HW
BIU - IP Abis
IP Abis
BIU
IPBB
BIPB2
TCU
GUP2
GUP2
GIPI
UDP
SCTP
User Plane
Switching
Network
GUP2
to CMP
UPU
External
Ethernet
Internal
Ethernet
HW
BIU - IPoE Abis

IPoE Abis
BIU
BIPB2
TCU
RTP
c UDP
GUP2
RTP
c UDP
GUP2
EIPI
32
DTB
ML/MC -PPP
PPP
HDLC
User Plane
Switching
Network
GUP2
SCTP
IP
UDP
UDP
to CMP
UPU
E1/T1
Internal
Ethernet
HW
Access Unit- A Interface Unit (AIU)
E1 A
E1 borne TDM link
IP A
FE/GE borne IP link
AIU - E1 A
E 1A
AIU
32
GUIM
GUP2
User Plane
Switching
Network
DTB
TCU
SPB2
Internal
Ethernet
1
2
16
E1/ T1
1
2
MTP2
HW
STM -1
AIU - IP A
IP A
AIU
IPI
AIPB
RTP
UDP
GUP2
GIPI
RTP
UDP
BIPB2
UDP
GUP2
SCTP
User Plane
Switching
Network
to CMP
External
Ethernet
Internal
Ethernet
HW
Access UnitGb Interface Unit (GIU)
E1 Gb
E1 borne TDM link
IP Gb
FE/GE borne IP link
GIU - E1 Gb
E 1 Gb
GIU
UPPB2
SPB2
GUP2
User Plane
Switching
Network
1
2
16
UDP
SPB2
1
2
16

to CMP
E1/ T1
Internal
Ethernet
GIU - IP Gb
IP Gb
GIU
UPPB 2
IPGB
GUP2
GIPI
UDP
UDP
BIPB 2
UDP
GUP2
User Plane
Switching
Network
to CMP
External
Ethernet
Internal
Ethernet
HW
O&M Unit
OMP Board
System operation and maintenance;

Connects to the iOMCR;
System management and monitoring
Switching Unit
OMPP
OMP
OMP
SBCX
SVB
100 M Ethernet
HH
UU
BB
LMT -R
Operation and Maintenance Networking
The networking mode of SBCX is as follows: iBSC and

SBCX(OMP1) form a subnetwork, and
SBCX(OMC1)+NetNumen for a subnetwork. The local
OMM usually consists of the SBCX and the SBCX client
(LMT).Usually, LMT and the OMM client are installed on
the same PC. The PC is then put in a different equipment
room. The network interfaces of SBCX are connected to
the switches of each iBSC, and then connected to the
router. Then the cables are connected to the remote
NetNument using WAN connection.
When the iBSC needs to manage SDR BTSs, the OMCB
server manages all SDR configurations (physical,
transmission and radio configurations), links, alarms and
versions. The OMCB program is installed on the SBCX
and a pair of GIPI boards must be configured.
Operation and Maintenance Networking
Processing Units & Monitoring Units
Processing Unit - CMPU
CMP Board
PS/CS Service Call and Control Management
BSSAP, BSSGP and System Resource Management
Monitoring Unit - PMU
PWRD board
The PWRD board collects the environment monitoring
information of peripheral devices, including temperature
and humidity, smoke, water and infrared alarms.
UPU & TCU
Processing Unit UPU
UPPB2: Processes PS protocols
TransCoder Unit TCU
DRTB2: code transfer and rate adaptation
IP Switch Unit (PSU)
Level 1 switch: GLI and PSN, 40G large-capacity user plane data switch.
Level 2 switch: UIMU,GUIM, UIMC, and CHUB, responsible for the switch
and convergence of control plane and user plane data in the system.
Switch
st
1 Switch Subsystem
Control
nd
Switch Subsystem
FE
2*GE
nd
2 Switch Subsystem
nd
Switch Subsystem
GE
FE
BGSN 1
BGSN N
IP Switch Unit (PSU)
If there are only two resource shelves, the Level-1 switch subsystem is not
needed on the user plane. The two resource shelves can be directly
interconnected using Gigabit optical interfaces.
Control
nd
Switch Subsystem
FE
nd
nd
Switch Subsystem
Switch Subsystem
2*GE
GE
FE
BGSN 1
BGSN 2
Contents

Plane
User Plane Signal Flow in the CS Domain
The BIU severs user plane data from control plane data, and then
sends user plane data to the TCU, which processes such data
and then sends it to the AIU. Signal flow 12.
UPU
TCU
2
Abis Interface
User plane
switch network
AIU
A Interface
BIU
Gb Interface
Control plane
switch network
CMP
GIU
OMP
User Plane Signal Flow in the PS Domain
The BIU severs CPU frames from all frames and sends them to
the UPU(UPPB2) through the user plane switching network. The
UPU then separates PS field user plane data from CPU frames
received for further processing. After data processing is complete,
the data is sent to the GUI through the user plane switching
network.
UPU
Abis Interface
TCU
User plane
Switching network
A Interface
AIU
BIU
Control plane
Switching network
CMP
GIU
OMP
Gb Interface
Control Plane Signal Flow in the CS Domain
Abis interface signal flow Abis interface unit (BIU) sends signaling in the
LAPD channel to the CMP board as control plane data. The CMP
processes such data and sends some of it directly back to the BIU (flow
direction: 11). Some signaling data will be sent to the AIU in the form of
A-interface signaling flow (flow direction: 12).
A-interface signal flow: The AIU processes the MTP2 part of A-interface
signaling, and then sends it to the CMP to complete the processing of
MTP3 and layers above. Some global processes need the participation
of the OMP. The data flow direction is 2332 or 22.
UPU
TCU
A Interface
User plane
Switching network
Abis Interface
AIU
2
BIU
Gb Interface
1
GIU
Control plane
Switching network
CMP
OMP
Control Plane Signal Flow in the PS Domain
For some control plane signaling in the PS field, the system requests
resources from the CMP board, and then sends the signaling to the
UPPB2 for processing.
When the MS is processing PS services, control plane signaling should
be separated from UPPB2 and then sent to the CMP for processing.
UPU
TCU
4
A Interface
User plane
Switching network
Abis Interface
AIU
BIU
3
1
5
GIU
Control plane
Switching network
CMP
OMP
Gb Interface
Abis interface signaling flow
The Abis interface unit (BIU) sends control plane data in

the LAPD channel to the CMP board. The CMP
processes such data and sends some of it directly back
to the BIU (flow direction: 11). Some data, such as
packet assignment messages, is sent to the UPU,
which processes the data and then sends it to the BIU
through the user plane switch network (flow direction:
132).
Data from the Abis interface unit is sent to the UPU
through the user plane switch network. The UPU
processes the data and separates control signaling
packets, which are sent to the control plane processing
board (CMP).The data flow direction is: 2332.
Gb interface signaling flow
The GIU sends BVC channel data as control plane data to the
active CMP. The CMP processes the data and sends some of it
(such as PTP BVC restart) to other CMPs and some (such as
signaling BVC restart) to the OMP. The CMP or the OMP
processes the data and some signaling generates the Abis
signaling traffic, such as paging messages in the PS or CS field,
whose data flow is 51 or 532; other signaling, such as PTP
BVC restart acknowledgement and signaling BVC restart
acknowledgement, is sent to the Gb interface through the GUI, with
the data flow as 55 or 66.
The GUI routes data from other BVC channels to the user plane
processing unit, which separates control plane data and sends it to
the CMP. The CMP processes the data and some signaling, such
as PTP paging messages, is sent to the Gb interface through the
GIU with the data flow as 435; some signaling generates the
Abis signaling flow, such as location messages, with the data flow
as 431.
User Plane Board Signal Flow in the CS Domain
E1 Abis, E1 A
The BIU severs user

plane data from control
plane data, and then
sends user plane data
to the TCU, which
processes such data
and then sends it to the
AIU.
Signal flow 12.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
HUB
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
CP
BIPB2
LAPD2
Circuit
DTB
GUIM
UIMU ( UIM _ 2 )
UP
DRTB2
CP
SPB2
Circuit
DTB
E1 Abis
E1 A
A
iOMCR Client
Control Plane Board Signal Flow in the CS Domain
E1 Abis, E1 A
The Abis interface unit

(BIU) sends signaling in
the LAPD channel to the
CMP board as control
plane data. The CMP
processes such data
and sends some of it
generates the A
interface signaling flow
to the AIU.
Signal flow 12.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
HUB
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
CP
BIPB2
LAPD2
Circuit
E1 Abis
DTB
GUIM
UIMU ( UIM _ 2 )
UP
DRTB2
CP
SPB2
Circuit
DTB
E1 A
iOMCR Client
User Plane Board Signal Flow in the CS Domain
IP Abis, IP A
The BIU severs user

plane data from control
plane data, and then
sends user plane data
to the TCU, which
processes such data
AIU.
Signal flow 12.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
HUB
CP
Circuit
IPBB
BIPB2
IP Abis
GUIM
UIMU ( UIM _ 2 )
UP
AIPB
CP
Circuit
IPI
IP A
iOMCR Client
Control Plane Board Signal Flow in the CS Domain
IP Abis, IP A

(BIU) sends signaling in
the LAPD channel to the
CMP board as control
plane data. The CMP
processes such data
and sends some of it
generates the A
interface signaling flow
to the AIU.
Signal flow 12.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
HUB
CP
Circuit
IPBB
BIPB2
IP Abis
GUIM
UIMU ( UIM _ 2 )
UP
AIPB
CP
Circuit
IPI
IP A
iOMCR Client
User Plane Board Signal Flow in the PS Domain
E1 Abis, E1 Gb
The BIU severs CPU

frames from all frames
and sends them to the
UPU(UPPB) through the
user plane switching
network. The UPU then
separates PS field user
plane data from CPU
frames received for
further processing. After
data processing is
complete, the data is
sent to the GUI through
the user plane switching
network.
Signal flow 12.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
BIPB2
HUB
CP
Circuit
LAPD2
E1 Abis
DTB
GUIM
UIMU ( UIM _ 2 )
UP
UPPB2
CP
Circuit
GIPB2
E1 Gb
iOMCR Client
Control Plane Board Signal Flow in the PS Domain
E1 Abis, E1 Gb

(BIU) sends control
plane data in the LAPD
channel to the CMP
board. The CMP
processes such data
and sends some of it to
the UPU (such as
packet assignment
message). The UPU
processes such data
BIU through the user
plane switch network.
Signal flow 132.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
HUB
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
CP
BIPB2
LAPD2
Circuit
E1 Abis
DTB
GUIM
UIMU ( UIM _ 2 )
UP
UPPB2
CP
Circuit
GIPB2
E1 Gb
iOMCR Client
E1 AbisE1 Gb
The GIU sends BVC

channel data as control
plane data to the main
CMP. The CMP
processes the data and
some signaling
generates the Abis
signaling flow, such as
paging messages in the
CS field
Signal flow 532.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
HUB
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
CP
BIPB2
LAPD2
Circuit
E1 Abis
DTB
GUIM
UIMU ( UIM _ 2 )
UP
UPPB2
CP
Circuit
GIPB2
E1 Gb
iOMCR Client
User Plane Board Signal Flow in the PS Domain
IP Abis, IP Gb
The BIU severs CPU

frames from all frames
and sends them to the
UPU(UPPB) through the
user plane switching
network. The UPU then
separates PS field user
plane data from CPU
frames received for
further processing. After
data processing is
complete, the data is
sent to the GUI through
the user plane switching
network.
Signal flow 12.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
HUB
CP
Circuit
IPBB
BIPB2
IP Abis
GUIM
UIMU ( UIM _ 2 )
UP
UPPB2
CP
Circuit
IPGB
IP Gb
iOMCR Client
IP Abis, IP Gb

(BIU) sends control
plane data in the LAPD
channel to the CMP
board. The CMP
processes such data
and sends some of it to
the UPU (such as
packet assignment
message). The UPU
processes such data
BIU through the user
plane switch network.
Signal flow 132.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
HUB
CP
Circuit
IPBB
BIPB2
IP Abis
GUIM
UIMU ( UIM _ 2 )
UP
UPPB2
CP
Circuit
IPGB
IP Gb
iOMCR Client
IP Abis, IP Gb
The GIU sends BVC

channel data as control
plane data to the main
CMP. The CMP
processes the data and
some signaling
generates the Abis
signaling flow, such as
paging messages in the
PS or CS field
Signal flow 532.
BPSN
BCTC
SBCX
PSN
UIMC
UIMC
OMP
GLI
GLI
CHUB
CMP
BGSN
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
HUB
CP
Circuit
IPBB
BIPB2
IP Abis
GUIM
UIMU ( UIM _ 2 )
UP
UPPB2
CP
Circuit
IPGB
IP Gb
iOMCR Client
IP over E1 Signal Flow
IPoE User Plane Signal Flow
BGSN
IPoE Control Plane Signal Flow
BGSN
GUIM
UIMU ( UIM _ 2 )
UP
CP
BIPB2
EUIP
Circuit
DTB
IPoE Abis
GUIM
UIMU ( UIM _ 2 )
UP
CP
BIPB2
EUIP
Circuit
DTB
IPoE Abis
Contents

Plane
System Interconnection Modes
Most boards are managed by the OMP via the internal control plane.
The CLKG/ICM board are connected to the UIMC via the RS485 bus,
and then managed by the OMP.
The PWRD board is directly managed by the OMP via the RS485 bus.
OMP
P
W
R
D
C
L
K
G
S
P
B
M
N
I
C
D
T
B
V
T
C
D
RS485
OMC-R
S
D
T
B
G
U
I
M
C
M
P
C
H
U
B
G
L
I
Ethernet
P
S
N
U
I
M
C
Internal Communications Management

BCTC in 1# Rack
BPSN
UIMC
OMP
485 Signal
GLI
UIMC
User
Plane
Ethernet
GUIM
BGSN1
User Plane Ethernet
CHUB
Control
Plane
Ethernet
CLKG
PWRD
in Each
Rack
CLKG
UIMC
GUIM
BGSN2
Circuit Switch
Shelf
System Clock Capture and Distribution

Principles
The CLK board is responsible for

supplying clock signals and
external synchronization
functions.
Clock level: Level 3 clock
The board extracts clock
reference via A Iu interface and
drives multiple channels of timing
reference signals for use by each
interface shelf after intra-board
synchronization.
Level 2 forwarding of the UIM
board
DTB, SDTB2 and SPB2 can be
used to extract line reference
The BPSN does not need a clock
reference
BITS interfaceLine 8K reference GPS reference

BCTC
ICM/CLKG
8K reference
8K 16M
8K 16M
Differential signals Differential signals Differential signals
BGSN
BPSN
GUIM
DTB
SPB2
UIMC
SDTB2
GLI
E1
GLI
STM-1
Intra-shelf Cable Connection
Clock extraction and distribution cables;

Control plane and Ethernet interconnection cables;
User plane optical cable connection;
Monitoring cable.
Clock Extraction and Distribution Cables
The clock extraction cable

connects the 8KOUT
interface on the DTB rear
board to the 8KIN interface
on the ICM.
The ICM can also extract
GPS signals as the clock
reference.
The clock distribution cables
connect the CLKOUT
interface on the ICM rear
board to the CLKIN
interfaces on UIM boards in
each shelf.
Power distribution subrack

Fan subrack
BGSN
G
U
I
M
BCTC
U
I
M
C
BGSN
G
U
I
M
BPSN
O
M
P
I
C
M
C
H
U
B
U
I
M
C
Control Plane and Ethernet Interconnection

Cables
The FE interfaces of the

CHUB rear boards connect
to the FE interfaces of the
UIM boards in each shelf.
Internal GE connection is
used inside the BCTC.

Fan subrack
BGSN
G
U
I
M
BCTC
U
I
M
C
BGSN
G
U
I
M
BPSN
O
M
P
I
C
M
C
H
U
B
U
I
M
C
User Plane Optical Cable Connection
The optical interface on the

GUIM front panel in the
BGSN connects to the
optical interface on the PLI
front panel.
Supports physical backup.

Fan subrack
BGSN
G
U
I
M
BCTC
U
I
M
C
BGSN
G
U
I
M
BPSN
G
L
I
O
M
P
I
C
M
C
H
U
B
U
I
M
C
Monitoring Cables
The cables between fans to PWRD

boards are usually 120 ohm
twisted-pair cables that are
connected to the FANBOX
interfaces to monitor fan running
status.
The environment monitoring sensor
is connected to the SENSORS
interface on the PWRD board to
collect environment alarms.
The door access sensor is
connected to the DOOR interface
on the PWRD board to monitor door
access status.
The PWRD board reports
monitoring information to the OMP
board via RS485 cables.
Sensor
Cabinet-top fan
Fan subrack
BGSN
G
U
I
M
BCTC
U
I
M
C
O
M
P
I
C
M
C
H
U
B
Fan subrack
G
U
I
M
BGSN
BPSN
U
I
M
C
G
L
I
Fan subrack

5.GB - SS42 - E2 - 1 ZXG10 IBSC Structure and Principle (1G) 118

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5.GB - SS42 - E2 - 1 ZXG10 IBSC Structure and Principle (1G) 118

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ZXG10 iBSC Structure and Principles

After learning this course, you will:

Understand the functions, features and specifications

iBSC System Overview

What does "i" stand for?

intelligent identification of wireless

ZXG10 iBSC Product Features

Based on V3 universal hardware platform

Universal All IP Hardware Platform

Different software can be used to define

The system can be

Multiple Access Modes and Smooth Evolution

iBSC supports multiple access modes

Saves 20% space when 2G and 3G

ZXG10 iBSC Interfaces

E1, STM-1, FE/GE

ZXG10 iBSC Interface Specifications

A:4 pairs of STM-1

Abis:9 pairs of STM-1

A:4 pairs of STM-1

Abis:9 pairs of STM-1

A:11 pairs of STM-1

A:11 pairs of STM-1

A:4 pairs of STM-1

ZXG10 iBSC Physical Specifications

Dimensions (H*D*W) (mm)

2,000 * 800 * 600

Power Source Requirements

-48V DC (-40V DC to -57V DC)

Long-term humidity: 2090%.

ZXG10 iBSC Performance Specifications

Maximum throughput over Gb

Maximum TRXs supported

One Rack: 1,024

The all-IP architecture conforms to the trend towards an IPbased network

Large capacity and strong processing capabilities

Supports E1, T1, STM-1 and IP interfaces and flexible

iBSC System Overview

Hardware Architecture Introduction

Abis IP over E1, E1, IP

Control Plane & User Plane

Control shelf (BCTC), resource shelf (BGSN), switch shelf

ZXG10 iBSC Shelves

control and management

capture and distribution

of control plane signaling

operation and maintenance

Resource Shelf (BGSN)

Switch Shelf (BPSN)

IP switch platform on the user plane

ZXG10 iBSC Boards

Level 2 switch of control plane signaling

Control and management of CS and PS services, processing of

Control Main Processor

Operation Main Processor

Operation and maintenance, system control, management and

X86 Single Board Computer

Clock generation and distribution

Integrated Clock Module

Clock generation and distribution (with GPS)

Gigabit Line Interface

Level 1 switch, interface with the resource shelf

Packet Switch Network

Dimensions (HDW) (mm)