Legend Logic Design

Department of Electrical and Computer Engineering
University of Waterloo
Number Systems and Information

Representation
Copyright 2005 by W. D. Bishop. All Rights Reserved
Decimal Number System

The decimal number system has a base of 10
When a quantity is written without a base specified, the
quantity is assumed to have a base of 10
Consider the quanity, 8 192:
8 192
= (8 192)10
= 8 103 + 1 102 + 9 101 + 2 100
For fractional quantities, negative exponents are used

Consider the quantity, 12.5:
12.5
= (12.5)10
= 1 101 + 2 100 + 5 10-1
December-10-14
Lecture Notes - SE 141: Digital Circuits and Systems

Digital Information Representation

The decimal number system is not ideal for representing
digital information in a digital computer system
Computers represent data using a binary (two-valued)
representation
Some binary representations of 0s and 1s are the following:

Representation of 0
Representation of 1
Voltage (e.g., 0 V)
Voltage (e.g., 3.3 V)
Current (e.g., 0 mA)
Current (e.g., 10 mA)
Switch Position (e.g., closed)
Switch Position (e.g., open)
Capacitor (e.g., discharged)
Capacitor (e.g., charged)
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Binary Number System

The binary number system has a base of 2
In binary, each digit is assigned a weight that is a power of 2
Powers of Two
n
2n
2n
2n
-8
0.00390625
256
-7
0.0078125
512
NOTE:
-6
0.015625
10
1024
-5
0.03125
11
2048
-4
0.0675
16
12
4096
-3
0.125
32
13
8192
-2
0.25
64
14
16384
This table is similar to

Table 1.1 in the
textbook. However, it
includes the negative
powers of two as well.
-1
0.5
128
15
32768
December-10-14


vs. Binary Number System
Binary Number System
Base 10
Base 2
Digits range from 0 to 9
Digits range from 0 to 1
Fewer digits are required to

represent large quantities
Many digits are required to

represent large quantities
Decimal vs. Binary Comparison Example
(8 192)10 = (1 0000 0000 0000)2

4 digits vs. 13 digits
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Important Powers of 2
There are certain powers of 2 that are easier to remember
due to their importance:
For example:
210 = 1 024
= Kilo
= (1 024)1
220 = 1 048 576
= Mega
= (1 024)2
230 = 1 073 741 824
= Giga
= (1 024)3
240 = 1 099 511 627 776
= Tera
= (1 024)4
December-10-14

Unsigned Binary Arithmetic

For now, assume that all binary numbers are unsigned
Unsigned binary arithmetic uses the same rules as decimal
arithmetic
Addition Example
Augend:
Addend:
Sum:
(1101 0110)2
(0011 0010)2
______________
(1 0000 1000)2
(214)10
(50)10
________
(264)10
Subtraction Example
Minuend:
Subtrahend:
Difference:
December-10-14
(1101 0110)2
(0011 0010)2
____________
(1010 0100)2
(214)10
(50)10
________
(164)10

Unsigned Binary Arithmetic

Multiplication simplifies to replicating and shifting the
multiplicand:
Multiplication Example
Multiplicand:
Multiplier:
Product:
December-10-14
(1010)2
(0110)2
________
(0000)2
(1 010)2
(10 10)2
(000 0)2
______________
(0011 1100)2
(10)10
(6)10
______
(0)10
(20)10
(40)10
(0)10
______
(60)10

Some Conversion Examples

(12.5)10
= (1100.1)2
(82.625)10 = (0101 0010.101)2

(0.0125)10 = (0.0000 0011 0001 1000 1100 011)2
The last conversion is quite ugly. The conversion algorithm is

shown on the next slide
December-10-14

Conversion of (0.0125)10 to Binary

Approximate Answer
Fraction Remaining
0.0125 2
= 0.025
(0.0)2
0.025
0.0250 2
= 0.05
(0.00)2
0.05
0.05 2
= 0.1
(0.000)2
0.1
0.1 2
= 0.2
(0.0000)2
0.2
0.2 2
= 0.4
(0.0000 0)2
0.4
0.4 2
= 0.8
(0.0000 00)2
0.8
0.8 2
= 1.6
(0.0000 001)2
0.6
0.6 2
= 1.2
(0.0000 0011)2
0.2
0.2 2
= 0.4
(0.0000 0011 0)2
0.4
0.4 2
= 0.8
(0.0000 0011 00)2
0.8
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10
Octal Representation
Octal is base 8
Digits range from 0 to 7 {0,1,2,3,4,5,6,7}
(1010 1011)2 = (253)8 = (171)10

2
Octal is rarely used

Octal representations may be used for specifying file permissions
in Unix-based systems
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11
Hexadecimal Representation
Hexadecimal is base 16
Digits range from 0 to F {0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F}
(1010 1011)2 = (253)8 = (171)10 = (AB)16

A
Hexadecimal is often used in C, C++, and C# to specify large

quantities (constants, addresses, etc.)
For example, 0xAB represents (171)10
Hardware designers sometimes use 0xDEAD as a 16-bit constant
to indicate a problem
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12
Complements
Complements of numbers are often useful to simplify
arithmetic
Two types of complements are popular:
Diminished Radix Complement (1s complement for binary)
Radix Complement (2s complement for binary)
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13
Diminished Radix Complement

Given a number N in base r having n digits, the diminished
radix complement is defined as (rn - 1) N
This is often called the (r-1)s complement
For the binary number system, the diminished radix

complement is referred to as the 1s complement
Complement of an 8-bit quantity N is (28 - 1) - N = 255 N
To calculate the 1s complement, simply complement each bit
For example, the 1s complement of (1010 0011)2 is (0101
1100)2
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14
Radix Complement
Given a number N in base r having n digits, the radix
complement is defined as rn N
This is often called the rs complement
For the binary number system, the radix complement is

referred to as the 2s complement
Complement of an 8-bit quantity N is 28 - N = 256 N
To calculate the 2s complement, simply complement each bit
and add 1 to the quantity
For example, the 2s complement of (1010 0011)2 is (0101
1101)2
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15
Subtraction with rs Complement

The subtraction of two n-digit unsigned numbers M - N in
base r can be done as follows:
1. Add the minuend, M, to the rs complement of the subtrahend, N
to produce an intermediate result. This performs M + (rn - N) =
M - N + rn.
2. If M N, the sum produces an end carry, rn, which can be
discarded. The final answer is M - N.
3. If M < N, the sum does not produce an end carry and the sum is
equal to rn - (N - M) which is the rs complement of (N - M). The
final answer is the negative rs complement of the sum.
December-10-14

16
Subtraction Example
Using 2s complement, subtract (1010)2 (0110)2
M
= (1010)2
= (0110)2
2s complement of N
= (1010)2
MN
= M + 2s complement of N (sort of)
(1010)2
2s complement of N
(1010)2
___________
Intermediate Result
= (1 0100)2
Final Answer
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(0100)2

NOTE:
The end carry
is discarded to
arrive at the
final result.
17
Subtraction Example 2
M
= (0110)2
= (1010)2
2s complement of N
= (0110)2
MN
(0110)2
2s complement of N
(0110)2
___________
Intermediate Result
(1100)2
Final Result
(0100)2
December-10-14
NOTE:
In this case, the
final answer is found
by taking the 2s
complement of the
intermediate result

18
Subtraction with (r - 1)s Complement

When using (r-1)s complement, the end carry is treated
differently
If M N, the end carry is truncated and 1 is added to the
intermediate result to produce the final answer
If M < N, the final answer is the negative (r - 1)s
complement of the intermediate result
December-10-14

19
Subtraction Example
M
= (1010)2
= (0110)2
1s complement of N
= (1001)2
MN
(1010)2
1s complement of N
(1001)2
____________
Intermediate Result
= (1 0011)2
Final Answer
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(0100)2

NOTE:
A value of 1 is
added to the result
to compensate for
the representation.
20
Signed Binary Numbers

Signed binary numbers can be represented three different
ways:
1. Signed Magnitude Representation
2. Signed 1s Complement Representation
3. Signed 2s Complement Representation
For example, (-36)10 can be represented in binary as follows:

1. (1010 0100)2 in signed magnitude representation
2. (1101 1011)2 in signed 1s complement representation
3. (1101 1100)2 in signed 2s complement representation
December-10-14

21
Comparison of Signed Binary Numbers

Decimal
Signed Magnitude
Signed 1s Complement
Signed 2s Complement
+7
0111
0111
0111
+6
0110
0110
0110
+5
0101
0101
0101
+4
0100
0100
0100
+3
0011
0011
0011
+2
0010
0010
0010
+1
0001
0001
0001
+0
0000
0000
0000
-0
1000
1111
N/A
-1
1001
1110
1111
-2
1010
1101
1110
-3
1011
1100
1101
-4
1100
1011
1100
-5
1101
1010
1011
-6
1110
1001
1010
-7
1111
1000
1001
-8
N/A
N/A
1000
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22
Important Observations
for Signed Binary Numbers
If the most significant bit is a 0, the number is positive
If the most significant bit is a 1, the number is negative
The signed binary number representation is irrelevant for the
purpose of determining whether a value is positive or
negative
December-10-14

23
Signed Arithmetic
Signed arithmetic obeys the same basic rules as unsigned
arithmetic
Carries beyond the width of the number representation should
be discarded
Width of number representation must be large enough to
avoid an overflow condition
Overflow occurs if both number possess the same sign and the
result possesses a different sign
Overflow can be accommodated by making the result 1 bit larger
December-10-14

24
Signed Arithmetic Examples

Consider the following examples:
Addition Example 1
Augend:
Addend:
Sum:
(0110)2
(1010)2
_________
(1 0000)2
Addition Example 2
(6)10
(-6)10
_____
(16)10
Discarding the carry

Sum:
(0000)2
(0)10
Augend:
Addend:
Sum:
(1110)2
(1010)2
_________
(1 1000)2
(-2)10
(-6)10
_____
(-8)10
Discarding the carry

Sum:
(1000)2
(-8)10
NOTE:
2s complement arithmetic has
been used in these examples.
December-10-14

25
Binary Coded Decimal (BCD)
Binary coded decimal is an

obvious representation of
decimal digits
BCD uses 4-bits to represent a
decimal digit
Bit patterns 1010 through
1111 are not used by BCD
BCD to decimal conversion is
trivial
December-10-14
Decimal Digit
BCD Digit
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

26
Unsigned BCD Addition

It is possible to add two numbers specified in BCD
To compensate for the unused bit patterns, a value of (6)10 is
added to each BCD digit greater than (9)10 to account for the
true value of carries between BCD digits
BCD addition is prone to errors when done by hand
December-10-14

27
Unsigned BCD Addition Example

BCD Carry
(1)BCD
(1)BCD
(0010)BCD
(1000)BCD
(0100)BCD
(284)10
(0110)BCD
(0111)BCD
(0110)BCD
(676)10
_____________
________________
Binary Sum
(1001)BCD
(1 0000)BCD
Add (6)10
(0110)BCD
(0110)BCD
_____________
BCD Sum
December-10-14
(1001)BCD
________________
(0110)BCD
_____________
(1010)BCD
_____________
(0000)BCD

__________
(960)10
__________
(960)10
28
Gray Code
Gray code is a binary code that minimizes the number of bits
that change values during incrementing or decrementing
Extremely useful code for systems that process continuous
signals (e.g., sampled analog signals) and for low-power
computer systems (e.g., cellular phones)
Fewer bits changing provides the following benefits:
1. Lower dynamic power consumption
2. Faster data transitions
3. Greater reliability of data
December-10-14

29
Gray Code
December-10-14
Decimal
Number
Gray
Code
Decimal
Number
Gray
Code
0000
1100
0001
1101
0011
10
1111
0010
11
1110
0110
12
1010
0111
13
1011
0101
14
1001
0100
15
1000

30
Gray Code vs. Ordinary Binary Code

Consider the example of a transition from (7)10 to (8)10:
Using an ordinary binary code, 4 bits change
For example, (0111)2 becomes (1000)2
Using a Gray code, only 1 bit changes

For example, (0100)2 becomes (1100)2
December-10-14

31
American Standard Code

for Information Interchange (ASCII)
ASCII is the standard binary code for alphanumeric
characters
Standard ASCII is a 7-bit code
Extended ASCII is a 8-bit code

Each alphanumeric character is assigned to a unique binary
code
For more information on ASCII,

refer to www.asciitable.com
December-10-14

32

Boolean Algebra and Logic Gates
Formal Definition of Boolean Algebra

A Boolean algebra satisfies the following postulates defined
by E. V. Huntington in 1904:
1. Closure
a) Closure with respect to the operator + (Addition Operator OR)
b) Closure with respect to the operator (Multiplication Operator AND)
2. Identity elements
a) An identity element with respect to +, designated by 0: x + 0 = 0 + x = x
b) An identity element with respect to , designated by 1: x 1 = 1 x = x
3. Commutation
a) Commutative with respect to +: x + y = y + x
b) Commutative with respect to : x y = y x
December-10-14

34
Formal Definition of Boolean Algebra

4. Distribution
a) is distributive over +: x (y + z) = (x y) + (x z)
b) + is distributive over : x + (y z) = (x + y) (x + z)
5. Complement
For every element x B, there exists an element x B (called the complement of
x) such that (a) x + x = 1 and (b) x x = 0
6. Two elements
There exists at least two elements x, y B such that x y
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35
Two-Valued Boolean Algebra

1. Closure
2. Identity elements
3. Commutation
4. Distribution
5. Complement
6. Two elements
December-10-14
x y B,
if x B and y B
x + y B,
if x B and y B
0+x=x,
if x B
1 x = x,
if x B
x + y = y + x,
if x B and y B
x y = y x,
if x B and y B
x (y + z) = (x y) + (x z),
if x, y, and z B
x + (y z) = (x + y) (x + z),
if x, y, and z B
x + x = 1,
if x B
x x = 0,
if x B
B = {0,1}

36
Differences with Ordinary Algebra

1. Associative law
2. Distributive law of + over only applies for Boolean algebra
3 + (2 5) (3 + 2) (3 + 5) in ordinary algebra
1 + (1 0) = (1 + 1) (1 + 0) in Boolean algebra
3. Boolean algebra does not have additive or multiplicative

inverses; therefore, there are no subtraction or division
operations
4. Complement only exists in Boolean algebra
5. Boolean algebra applies to a finite set of elements
December-10-14

37
Theorems of Two-Valued Boolean Algebra

Theorem 1(a):
x+x=x
Theorem 1(b):
xx=x
Theorem 2(a):
x+1=1
Theorem 2(b):
x0=0
Theorem 3:
(x) = x
continued
December-10-14

38
Theorems of Two-Valued Boolean Algebra

Theorem 4(a):
x + (y + z) = (x + y) + z
Theorem 4(b):
x (y z) = (x y) z
Theorem 5(a):
(x + y) = x y
Theorem 5(b):
(x y) = x + y
Theorem 6(a):
x + xy = x
Theorem 6(b):
x(x + y) = x
December-10-14

39
Duality
To determine the dual of an algebraic expression, simply
interchange OR and AND operators and replace 1s by 0s and
0s by 1s
Duality is used to derive Theorem 2(b) and Theorem 6(b)
Duality is an extremely powerful concept, particularly when
proving complex theorems involving constants
Example:
f = xyz + xy
dual of f = (x + y + z)(x + y)
December-10-14

40
DeMorgans Theorem
Theorems 5(a) and 5(b) are commonly referred to as
DeMorgans Theorem
Proof of DeMorgans Theorem is too long to produce on a slide
However, it is possible to show that it works using truth

tables as follows:
December-10-14
(x + y)
x y

41
Digital Logic Gates
Buffer
Inverter
f
f=x
AND
x
y
December-10-14
f = x
f = (x y)
NAND
f
f=xy
x
y

42
Digital Logic Gates
OR
x
y
NOR
f
f=x+y
x
y
XOR
x
y
December-10-14
f = (x + y)
XNOR
f
f=xy
x
y

f = (x y)
43
Digital Logic Gate Truth Tables

x
Buffer
Inverter
AND
NAND
OR
NOR
XOR
XNOR
NOTE:
For the buffer and the inverter, only the input x is
relevant. Thus, the results have been duplicated.
December-10-14

44
Implementing Boolean Functions with Digital

Logic Gates
Given a Boolean function f of 1 or more input variables, it is
possible to draw an equivalent logic gate implementation for f
Example:
f = xy + xz
y
x
f
z
December-10-14

45
Implementing Boolean Functions with Digital

Logic Gates
It should be noted that the functions f1 = xy and f2 = xz are
both found within the digital logic gate implementation of
function f
NOTE:
Recall:
f = xy + xz
y
x
z
December-10-14
= f1 + f2
f1
f1 and f2 are examples

of intermediate nodes.
f2

46
Truth Tables for Boolean Functions

Similarly, it is possible to construct a
truth table for the function f
Example:
f = xy + xz
y
x
f
z
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47
Simplifying Digital Circuits

Sometimes, a direct
translation of a Boolean
function is not the best
approach
Consider Fig. 2-2 from

Mano shown to the right
F2 can be implemented
in the two ways shown
(and perhaps many
more)
Implementation (b) uses
fewer gates and wires
December-10-14

48
Algebraic Manipulation of Boolean Functions

Boolean algebra can be used to simplify Boolean functions
Boolean functions consist of terms and literals
A term (e.g., xy) requires a logic gate and each variable within a
term acts as an input to the logic gate
A literal is a single variable within a term
Consider the functions f1 and f2:
f1 = xyz + xy + yz
3 terms and 7 literals
f2 = xy + xz
2 terms and 4 literals
Algebraic manipulation is used to reduce the number of terms

and literals in the hope of designing a simpler circuit
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49
Examples of Algebraic Manipulation

x(x + y + z) = xx + xy + xz
= 0 + xy + xz
= xy + xz
xy + xz + yz = xy + xz + yz(x + x)
= xy + xz + xyz + xyz
= xy(1 + z) + xz(1 + y)
= xy + xz
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50
Complement of a Boolean Function

DeMorgans Theorem applies to functions of two variables,
however, it can be extended to Boolean functions as well
(x + y + z)
December-10-14
= (x + a)
Let a = y + z
= xa
By DeMorgans Theorem 5(a)
= x(y + z)
Substituting for a
= x(yz)
By DeMorgans Theorem 5(a)
= xyz
By Theorem 4(b)

51
DeMorgans Theorem Revisited

In general, the following is true for Boolean functions of n
variables:
(x1 + x2 + x3 + + xn) =
x1x2x3xn
(x1x2x3xn)
x1 + x2 + x3 + + xn
DeMorgans Theorem is an extremely important theorem that

is useful in the algebraic manipulation of Boolean functions
December-10-14

52
More Comments on the Applications of Duality

Duality can be used to simplify Boolean expressions but not
individual terms
Dual of a function f and the function f itself are not equivalent
If duality is applied to a Boolean expression, the expression
remains true
Examples:
Given:
x+y=y+x
xy = yx
Given:
x(y + z) = xy + xz
x + yz = (x + y)(x + z)
December-10-14
By applying duality
By applying duality

53
Duality
Applying duality changes an expression
Changes to the LHS (Left-Hand Side) of the expression are
equivalent to the changes to the RHS (Right-Hand Side) of
the expression
Clearly, f Dual of f
Example:
x y
=y+x
Dual of f
= yx
December-10-14
Dual of f
0 0 0
0 1 1
1 0 1
1 1 1

54
Digital Logic Gate Equivalents

It is possible to build an inverter using a single NAND gate or
a single NOR gate
In fact, it is possible to build any combinational circuit using
only NAND gates or NOR gates
o1
o2
December-10-14
o1 o2 o3
o3

55
More Logic Gate Equivalents

By moving inversions from the output of a logic gate to the input of
a logic gate, it is possible to transform from one logic gate to an
equivalent logic gate
This is an application of DeMorgans Theorem
i1
i2
i1
i2
December-10-14
o1
i1
i2
o2
i1
o3
i2
o4
i1
i2
o1 o2 o3 o4

56
More Logic Gate Equivalents

OR gates become NAND gates (and vice-versa)
NOR gate become AND gates (and vice-versa)
i1
i2
i1
i2
December-10-14
i1
o1
i2
o2
i1
o3
i2
o4
i1
i2
o1 o2 o3 o4

57
Canonical Forms
A canonical form is a standard way of expressing a Boolean
function that produces a unique and predictable algebraic
structure
Two types of two-level canonical forms exist:
Sum of Products (Disjunctive Normal Form)
Product of Sums (Conjunction Normal Form)
Canonical forms are not often the most compact

representation of a Boolean function
Canonical forms and truth tables have a one-to-one
relationship:
Given a truth table, it is easy to represent the truth table in the
two canonical forms
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58
Minterms
Sum of products form uses the
notion of a minterm
x y z Minterm Designation
0 0 0
xyz
A minterm is an AND term with

every input (or its complement)
m0
0 0 1
xyz
m1
0 1 0
xyz
m2
For n inputs, there exist 2n

minterms
0 1 1
xyz
m3
1 0 0
xyz
m4
1 0 1
xyz
m5
1 1 0
xyz
m6
1 1 1
xyz
m7
Each minterm has a designation
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59
Canonical Sum of Products Form

Given a truth table, it is possible to write the expression for the
output (and its complement) in canonical sum of products form
Example:
f
x y
Minterm
0 0
m0
0 0
m1
0 1
m2
0 1
m3
= m0 + m3 + m4 + m6
1 0
m4
= xyz + xyz + xyz + xyz
1 0
m5
1 1
m6
1 1
m7
= (1,2,5,7)
= m1 + m2 + m5 + m7
= xyz + xyz + xyz + xyz
f = (0,3,4,6)
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60
Maxterms
Product of sums form uses the
notion of a maxterm
x y z
Maxterm
Designation
0 0 0
x+y+z
A maxterm is an OR term with

every input (or its complement)
M0
0 0 1
x + y + z
M1
0 1 0
x + y + z
M2
For n inputs, there exist 2n

maxterms
0 1 1 x + y + z
M3
1 0 0
x + y + z
M4
1 0 1 x + y + z
M5
1 1 0 x + y + z
M6
1 1 1 x + y + z
M7
Each maxterm has a

designation
NOTE:
The maxterms can be found by
applying DeMorgans Theorem
to the minterms
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61
Canonical Product of Sums Form

Given a truth table, it is possible to write the expression for the
output (and its complement) in canonical product of sums form
Example:
f
x y z
Maxterm
0 0 0
M0
0 0 1
M1
0 1 0
M2
0 1 1
M3
= M1 M2 M5 M7
1 0 0
M4
= (x + y + z)(x + y + z)(x + y + z)(x + y + z)
1 0 1
M5
1 1 0
M6
1 1 1
M7
= (0,3,4,6)
= M0 M3 M4 M6
= (x + y + z)(x + y + z)(x + y + z)(x + y + z)
f = (1,2,5,7)
December-10-14

62
Converting Between Canonical Forms

When converting between canonical forms, interchange the
symbols and and list the numbers missing from the
original form
Examples:
Example 1: f(x,y,z)
= (1,3,6)
= (0,2,4,5,7)
Example 2: f(x,y,z)
= (0,2,4,6)
= (1,3,5,7)
December-10-14

63
Standard Forms
Canonical forms are awkward at times:
Each minterm (or maxterm) contains all inputs or input
complements
For large numbers of inputs, canonical forms can result in large
expressions
Standard form may contain any number of literals

Standard forms exist in two forms (sum of products and product
of sums)
Example:
f = xyz + xyz + xyz + xyz Canonical Form
f = yz + xyz + xyz
Standard Form
Canonical form and standard form are examples of two-level

implementations
December-10-14

64
Two-Input Logic Gates

Given two inputs x and y, there are 4 input combinations
(00,01,10,11)
Therefore, there are 24 possible functions of two inputs
All 16 possible functions, labeled F0 to F15, are shown below:

x
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
0 0 0
0 1 0
1 0 0
1 1 0
December-10-14

65
Boolean Functions of Two Variables

Boolean
Function
Operator
Symbol
F0 = 0
Name
Comments
Null
Always 0
F1 = xy
xy
AND
x and y
F2 = xy
x/y
Inhibition
x but not y
Transfer
x (Error in textbook)
Inhibition
y but not x
Transfer
F3 = x
F4 = xy
y/x
F5 = y
F6 = xy + xy
xy
XOR
x or y, but not both
F7 = x + y
x+y
OR
x or y
December-10-14

66
Boolean Functions of Two Variables

Boolean
Function
Operator
Symbol
F8 = (x + y)
xy
F9 = xy + xy
(x y)
F10 = y
F11 = x + y
F12 = x
y
xy
x
Name
Comments
NOR
Not x or y
XNOR
x equals y
NOT
Not y
Implication
If y, then x
NOT
Not x
F13 = x + y
xy
Implication
If x, then y
F14 = (xy)
xy
NAND
Not x and y
Identity
Always 1
F15 = 1
December-10-14

67
Functionally Complete Sets of Logic Gates

It is possible to implement any digital logic circuit using
combinations of the following sets of gates
1. {AND, NOT}
2. {OR, NOT}
3. {NAND}
4. {NOR}
A set of gates that can implement all functions of two-inputs

is said to be functionally complete
The choice of a functionally complete set of gates depends
upon the target hardware technology
December-10-14

68
Comments on NAND and NOR Gate

Implementations
NAND and NOR gate implementations tend to be most
efficient
Require less area on a computer die (chip)
Consume less power
Transition faster
AND and OR gate implementations tend to be less efficient

Given a choice, designers should consider translating Boolean
functions to NAND implementations
Two-level implementations of sum of products functions can
be easily translated to two-level NAND implementations
December-10-14

69
Translation Example
x
y
x
y
f = xy + xy
x
y
f
x
y
f = xy + xy
NOTE:
To switch to NAND gates when using a two-level, sum of products form,
simply switch all of the AND and OR gates to NAND gates. This is a
special case!
December-10-14

70
Logic Levels
Digital logic gates operate on voltage signals, not logic values
How do you represent a Boolean value using voltage?
1. 0 V = 0,
5V=1
2. < 0.5 V = 0,
> 4.5 V = 1
3. < 0.5 V = 0,
> 2.5 V = 1
4. 5 V = 0,
0V=1
5. > 4.5 V = 0,
< 0.5 V = 1
6. > 2.5 V = 0
December-10-14
< 0.5 V = 1
Positive Logic
Negative Logic
NOTE:
The actual voltage thresholds
depend upon the technology
used.

71
Positive Logic vs. Negative Logic

With positive logic
Low (L) signal values represent a 0
High (H) signal values represent a 1
With negative logic

Low (L) signal values represent a 1
High (H) signal values represent a 0
Positive Logic
Negative Logic
Logic
Value
Signal
Value
Logic
Value
Signal
Value
December-10-14

72
Polarity Indicators
Truth tables for digital gates
often use L and H rather than 0
and 1
Polarity Indicator
Hardware designer must know

the implementation technology
to understand what L and H
really mean
Polarity indicators can be used
on a digital logic gate to
identify negative logic signals
December-10-14
Negative Logic OR Gate

x

73
Acronyms
SSI: Small-Scale Integration
10 or fewer gates in a single package
MSI: Medium-Scale Integration

10 to 1,000 gates in a single package
LSI: Large-Scale Integration

1,000 to 100,000 gates in a single package
VLSI: Very Large-Scale Integration

100,000+ gates in a single package
ASIC: Application-Specific Integrated Circuit

Custom integrated circuit for a specific application
December-10-14

74

Programmable Logic Devices and Memory
Part I
Introduction to Memory Units

and Programmable Logic Devices
Memory units and programmable logic devices are
similar in function
Given a set of inputs, deliver a set of outputs
Effectively act as lookup tables (LUTs)

For example, a 3-input truth table may be
implemented (trivially) in a read-only memory
(ROM) with 3 address bits:
A0
A1
A2
December-10-14
ROM
D0
y
z
LUT

76
Memory Units
December-10-14

77
Classification of Programmable Logic Devices
December-10-14

78
PAL Block Diagram

NOTE:
To simplify the
diagram, only one
signal is shown
connecting with
each of the AND
gates but each AND
gate can have
several input
signals.
December-10-14

79
Field Programmable Gate Arrays

Field programmable gate arrays provide a combination of
lookup tables (LUTs), RAM, and I/O functionality
Many different variations on FPGAs exist
Xilinx 4000 Series FPGA (now obsolete) is a good example of

a simple FPGA
December-10-14

80
Xilinx 4000 Series Family FPGA Block Diagram
December-10-14

81
Xilinx 4000 Series CLB
December-10-14

82
Xilinx 4000 Series Input / Output Block (IOB)
December-10-14

83
FPGAs vs. ASICs

FPGAs are best suited for the rapid prototyping of digital logic
designs:
Proof of concept designs
Low production volume designs
ASICs are best suited for the development of low cost, mass
market digital logic designs and mixed signal (analog and
digital) designs
Designs that can recover the non-recurring engineering costs
High production volume designs
To view the Xilinx website for the Spartan IIE series of FPGAs,
click here
December-10-14

84

Gate Level Minimization
Karnaugh Maps
Simplification of Boolean expressions using algebraic
manipulation can be time consuming
Hardware designers often simplify Boolean expressions using
a graphical technique based on the use of a Karnaugh map
(K-map)
A Karnaugh map is an alternative way for representing the
truth table of a digital logic circuit
Generic Two-Input Karnaugh Maps

y
x
December-10-14
y
x
m0 m1
xy xy
m2 m3
xy
xy

86
Karnaugh Map Example

Karnaugh maps show visually
all possible expressions for a
particular truth table
Consider the following OR Gate
example:
OR Gate
Truth Table
x
December-10-14
Karnaugh Map
y
Standard Form: f = x + y
Canonical Form: f = xy + xy + xy

87
Rules for Gate-Level Minimization Using

Karnaugh Maps
1. All 1s in the Karnaugh Map need to be covered
2. For the simplest Boolean expression, the largest groupings of
1s should be picked
Valid groups of bits are groups of size 1, 2, 4, 8, 16, , 2n bits
Valid groups form rectangles
Rectangles can wrap around the Karnaugh Map
3. Overlapping of rectangles is allowed

4. Use Gray coding for bit groupings (e.g., {00, 01, 11, 10})
December-10-14

88
Gate-Level Minimization
Using Karnaugh Maps
yz
wx
00 01 11 10
00
01
11
10
yz
wx
00 01 11 10
00
01
11
10
December-10-14
NOTE:
These 4 bits could not be
grouped together as one term
f = wyz + wxy + xyz
NOTE:
These 4 bits can be
grouped together as one term
f = xz

89
Example 3-1 from the Textbook
December-10-14

90
December-10-14

91
December-10-14

92
Implicants and Prime Implicants

An implicant is any valid grouping in a Karnaugh Map
A prime implicant is any valid grouping in a Karnaugh Map
that is not a subset of another valid grouping
Essential prime implicants are those that cover at least one

minterm not covered by another prime implicant
Some minterms may be covered by several prime implicants
December-10-14

93
Number of Literals in a Term
December-10-14
Number of
Adjacent
Squares
Number of Literals in a
Term in an n-variable
Map
2k
n=2 n=3 n=4 n=5
16
32

94
Product of Sums Simplification

Karnaugh maps can be used to expression a function f in a
sum of products form or a product of sums form
For a sum of products, the function f is equal to the sum of all
minterms that produce a 1.
For a product of sums, the function f is equal to the sum of
all minterms that produce a 0.
Using DeMorgans Theorem, it is possible to convert a sum of
products expression for f into a product of sums expression for f
December-10-14

95
Sum of Products Using Karnaugh Maps

yz
wx
00 01 11 10
00
NOTE:
01
11
Recall this example.
10
yz
wx
00 01 11 10
00
01
11
10
December-10-14
f = wyz + wxy + xyz
NOTE:
Recall this example.
f = xz

96
Product of Sums Using Karnaugh Maps

yz
wx
00 01 11 10
00
01
11
10
f = y + wx + xz + wz
f = (y)(w + x)(x + z)(w + z)
NOTE:
yz
wx
00 01 11 10
00
01
11
10
December-10-14
f = x + z
f = xz
Both the function f and f

are shown for clarity. For
a product of sums
representation, the 0s are
circled to find f. Using
DeMorgans Theorem, f is
then determined.

97
Using Algebraic Manipulation

It is possible to show that the sum of products and product of
sums expressions are equivalent.
In other words, the following is true:
(y)(w + x)(x + z)(w + z)
= wyz + wxy + xyz
Proof:
(y)(w + x)(x + z)(w + z)
= (wy + xy)(wx + wz + xz + z)
= wxy + wxy + wyz + wxyz + wxyz + xyz + wyz + xyz
= wxy + wyz + wxyz + xyz
= wyz + wxy + xyz
December-10-14

98
Five-Variable Karnaugh Maps

Rather than write large Karnaugh maps in one large matrix, it
is possible to split Karnaugh maps into two or more tables
For five-variable Karnaugh maps, it often makes sense to split
the map into two tables as shown below:
December-10-14

99
December-10-14

100
Comments on Splitting Karnaugh Maps

You must be very careful if you split a Karnaugh map
Example 3-7 illustrates an important simplification to note:
BDE appears in the Karnaugh Map for both A = 0 and A = 1
F = ABE + ACE + ABDE + ABDE
F = ABE + ACE + BDE
It is very easy to miss this simplification!
December-10-14

101
Dont Care Conditions

Sometimes, the output of a function really doesnt matter
Example of a Dont Care Condition:
Consider a digital circuit that outputs two signals. The first
signal indicates whether the digital circuit is enabled or not.
The second signal represents the output of the digital circuit
when enabled.
In this situation, the second signal is irrelevant if the first
signal indicates that the digital circuit is disabled. In this
case, the second signal and the output signal are in dont care
conditions.
December-10-14

102

In a truth table, dont care conditions are represented by an X
Two possible truth tables for the example of a dont care
condition discussed previously are shown below:
x y
x y
0 0 X
0 1 X
1 0 0
1 1 1
OR
0 X X
1 0 0
1 1 1
NOTE:
Dont care conditions are sometimes
indicated by the use of a -.
December-10-14

103

In a Karnaugh map, dont care conditions are represented by
the letter X
The Karnaugh map for the example of a dont care condition
discussed previously is shown below:
y
x
0 1
0 X X
1 0 1
This Karnaugh map can be represented by several functions:

f=y
Transfer
f = (x y)
XNOR
f = xy
AND
December-10-14

104
Importance of Dont Care Conditions

Dont care conditions introduce design flexibility
When writing a truth table (or a Karnaugh map), always use
an X for an output if a dont care condition exists
A dont care condition can be treated as either a 0 or a 1

during simplification
December-10-14

105
Evaluating Dont Care Conditions

Dont care conditions cannot be simultaneously treated as a 0
and a 1
In other words, if one term requires the value to be a 1, then it is
treated as a 1 for ALL terms
All dont care conditions should be considered independently

Some may be treated as a 1 while others may be treated as a 0
For large numbers of dont care conditions, the number of

prime implicants to consider can be quite large
EDA (Electronic Design Automation) tools such as Xilinx ISE
can evaluate dont care conditions to determine the simplest
implementation possible
December-10-14

106
December-10-14

107
Example 3-9 as a Product of Sums
f = z + wy
Complement of f
f = z(w + y) Product of Sums

f = wz + yz
December-10-14

Sum of Products
108
Comments on Boolean Functions

Any Boolean function can be expressed using a combination
of AND, OR, and NOT gates.
The reasoning for this is the following:
1. Any Boolean function can be expressed using a truth table
2. Any truth table can be expressed as a sum of products
3. Any sum of products can be converted to a combination of AND,
OR, and NOT gates
Both NAND gates and NOR gates are capable of implementing

AND, OR, and NOT gates
Hence, NAND gates and NOR gates implement a functionally
complete set of gates.
December-10-14

109
NAND Implementations of AND, OR, and NOT

Gates
x
NOT Gate
f = x
x
y
x
f
y
December-10-14
AND Gate
f = ((xy)) = xy
OR Gate
f = (xy) = x + y

110
NOR Implementations of AND, OR, and NOT

Gates
x
NOT Gate
f = x
x
y
OR Gate
f = ((x + y)) = x + y
x
f
AND Gate
f = (x + y) = xy
December-10-14

111
Interesting Properties of XOR Gates

XOR gates have the following interesting properties:
x0=x
x 1 = x
xx=0
x x = 1
x y = x y = (x y)
xy=yx
x y z = (x y) z = x (y z)
December-10-14

112
Uses of XOR Gates

Arithmetic operations
Error-detection and correction (parity generation)
December-10-14

113
Two-Input XOR and XNOR Gates
NOTE:
The course material on XOR and XNOR gates has been
adapted from the course notes for ECE 223 provided by
Dr. Andrew Kennings
December-10-14

114
Two-Input XOR Implementation Using AND, OR,

and NOT Gates
x
xy
December-10-14

115
Two-Input XOR Implementation Using NAND

Gates
x
xy
December-10-14

116
Four-Input XOR and XNOR Gates
December-10-14

117
Karnaugh Maps for Four-Input

XOR and XNOR Gates
x1x2
x3x4
December-10-14
00
01
11
10
00
01
11
10
x1x2
x3x4
00
01
11
10
00
01
11
10

118
Example of XOR Extraction

Given a Boolean function f, is it possible to simplify this
complex sum of products function using XOR and XNOR
gates?
Consider the following Karnaugh Map:
x1x2
x3x4
00
01
11
10
00
NOTE:
01
This Boolean function uses six

terms in sum of products form.
11
10
December-10-14

119
Example of XOR Extraction

x1x2
x3x4
00
01
11
10
00
01
11
10
XNOR
December-10-14

XOR
120
Example of XNOR Extraction

Simplifying
Arguably, this simplified expression using two XOR gates will

require fewer total gates to implement the function
QUESTION:
How do you find the optimal solution?
December-10-14

121
Optimal Gate Implementations

If nothing else, the previous example should make it clear
that optimal gate implementations are not easy to determine
Many alternative implementations exist
Direct evaluation of every alternative is intractable for most
practical applications
The problem of finding an optimal solution becomes more

complex if there are many outputs to be considered
May be possible to reuse intermediate nodes to reduce the
number of gates required
Must consider all outputs simultaneously
To further complicate the problem, fewer gates and literals

does not necessarily lead to a better design
December-10-14

122
Synthesis and Logic Optimizations

Synthesis tools use heuristics to obtain near-optimal
solutions
Fast logic synthesis is an active area of research
Fast logic synthesis becomes more challenging every year given
the trend of digital circuits growing in complexity at an
exponential rate
Fast heuristic solvers are essential
December-10-14

123
Example of Reuse of Intermediate Nodes

Consider the following functions f1 and f2:
f1 = x + y
f2 = xz + yz
A simple solution is the following:
x
x
y
f1
f2
December-10-14

124
Example of Reuse of Intermediate Nodes

Consider the following functions f1 and f2:
f1 = x + y
f2 = xz + yz = (x + y)z
A more advanced solution is the following:
f1
f2
December-10-14

125

Combinational Logic Design
Combinational Circuits
Combinational circuits consist of inputs, logic gates, and
outputs
Combinational circuits may be described by a truth table or m
Boolean functions
December-10-14

127
Analyzing Combinational Circuits

To determine the Boolean functions represented by a
combinational circuit, perform the following steps:
1. Label all gate outputs that are a function of input variables with
arbitrary symbols. Determine the Boolean functions for each
gate output.
2. Label the gates that are a function of input variables and
previously labelled gates with other arbitrary symbols. Find the
Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of the
circuit are obtained.
4. By repeated substitution of previously defined functions, obtain
the output Boolean functions in terms of input variables.
December-10-14

128
Example of Analyzing a Combinational Circuit

NOTE:
Step 1 adds labels
T1, T2, T4, T5, and T6
to to the diagram.
Step 2 is repeated to
label F2, F2, T3, and
F1 in order.
T4
T5
Step 4 is performed
to find the Boolean
functions in terms of
inputs.
T6
December-10-14

129
Determining the Boolean Functions

The combinational circuit on the previous slide contains two
outputs that need to be expressed as Boolean functions of the
three inputs
To express these functions, Boolean functions for each
intermediate node (T1, T2, T3, T4, T5, T6, and F2) must be
determined
December-10-14

130
Determining the Boolean Functions for Each

Logic Gate
F1 = T2T3
F2 = T4 + T5 + T6
T1 = A + B + C
T2 = ABC
T3 = T1F2
T4 = AB
T5 = AC
T6 = BC
F2 = (F2)
December-10-14

131
Determining the Boolean Function for F1

F1
= T2 + T3
= ABC + T1F2
= ABC + (A + B + C)(F2)
= ABC + (A + B + C)(T4 + T5 + T6)
= ABC + (A + B + C)(AB + AC + BC)

= ABC + (A + B + C)(A + B)(A + C)(B + C)
= ABC + (AB + AC + AB + BC)(AB + BC + AC)
= ABC + ABC + ABC + ABC
December-10-14

132
Determining the Boolean Function for F2

F2
=T4 + T5 + T6
= AB + AC + BC
Question:
What combinational circuit is shown in this example?

Answer:
The combinational circuit implements a 1-bit full adder:
A and B are single-bit inputs and C is the carry-in
F1 is the sum and F2 is the carry-out
December-10-14

133
Full Adder Truth Table

A full adder circuit performs 1-bit
addition
F1 F2
The inputs to the circuit are A, B, and

C (carry-in)
The outputs of the circuit are F1 (sum)

and F2 (carry-out)
The truth table shown to the right

describes a 1-bit addition circuit
December-10-14

134
Comments on the Full-Adder Circuit

Alternative implementations of the full-adder circuit exist
Full-adders are very practical circuits
It is possible to implement n-bit adders using n full-adder circuits
However, for large values of n, the carry chain becomes very
long
We will revisit the full-adder circuit shortly
December-10-14

135
Design Procedure
To design a combinational circuit from a specification of a
problem, perform the following steps:
1. From the specifications of the circuit, determine the required
number of inputs and outputs and assign a symbol to each.
2. Derive the truth table that defines the required relationship

between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a
function of the input variables.
4. Draw the logic diagram and verify the correctness of the design.
December-10-14

136
Textbook Example
Design a combinational circuit to convert from BCD code to
Excess-3 code
Step 1: Determine the inputs and outputs of the circuit
Four inputs labelled A, B, C, and D
Four outputs labelled w, x, y, and z
The label names were chosen arbitrarily in this case
December-10-14

137
Step 2: Truth Table

Input BCD Code
Output Excess-3 Code
December-10-14

138
Step 3: Boolean Simplification
December-10-14

139
Step 4: Logic Diagram
December-10-14

140
The Half Adder

C
Half Adder
(HA)
S
A B C S
0
0 0 0
1 0 1
0 0 1
1 1 0
NOTE:
From the truth table, it can be
seen that S = A B and C = AB
December-10-14

141
Implementations of the Half Adder

A
B
A
B
A
B
A
B
A
B
Implementation 1
Implementation 2
S = AB + AB
C = AB
S=AB
C = AB
December-10-14

142
The Full Adder

Ai
Ci+1
Bi
Full Adder
(FA)
Si
December-10-14
Ci
Ai
Bi
Ci
Ci+1
Si

143
The Full Adder

Recall that a full adder can be built as follows:
NOTE:
December-10-14

Ai
Bi
Ci
=A
=B
=C
Si
Ci+1
= F1
= F2
144
The Full Adder

However, the full adder can also be built as follows:
Half Adder
(HA)
Ci+1
Half Adder
(HA)
Si
December-10-14
Ai
Bi
Ci
Ai
Bi
Ci
Ci+1
Si

145
4-Bit Ripple Carry Adder

It is possible to build a 4-bit binary addition circuit using 4 full
adders as follows:
A3 B3
C4
Full Adder
(FA)
A2 B2
C3
Full Adder
(FA)
S3
C2
S2
A0 B0
C1
Full Adder
(FA)
Full Adder
(FA)
S1
C0
S0
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Ci
Augend
Ai
Addend
Bi
Sum
Si
Input Carry
December-10-14
A1 B1

146
4-Bit Ripple Carry Adder Subtractor

Recall that the A B = A + BTwos
Complement
B may be complemented (if necessary) using an XOR gate

Let a value of M = 0 represent addition
Let a value of M = 1 represent subtraction
Bi M = Bi, if M = 0
Bi M = Bi, if M = 1
The twos complement of B can be calculated by adding one

to the ones complement of B
M (defined above) can be used as the carry input
December-10-14

147
4-Bit Ripple Carry Adder Subtractor

It is possible to build a 4-bit binary addition and subtraction
circuit using 4 full adders as follows:
M
B3
B2
A3
C
C4
B1
A2
Full Adder
(FA)
S3
C3
Full Adder
(FA)
S2
B0
A1
C2
Full Adder
(FA)
A0
C1
S1
Full Adder
(FA)
C0
S0
December-10-14

148
4-Bit Ripple Carry Adder Subtractor Comments

The digital circuit shown on the previous slide is applicable for
both unsigned and signed arithmetic
M represents a mode input
M = 0 implies addition
M = 1 implies subtraction
C represents an overflow flag in the case of unsigned

arithmetic
V represents an overflow flag in the case of signed arithmetic
December-10-14

149
Carry Chains
Ripple carry adders and subtractors are inefficient for large
quantities
Ripple carry adders and subtractors use a carry chain
Carry resulting from the addition of the least significant bits must
be calculated before the addition of more significant bits can be
performed
Carry chains result in a propagation delay that is proportional

to the value of n for n-bit quantities
For an n-bit adder, there are 2n gate levels required for the
carry to propagate from the input to the output
Carry propagation is a limiting factor for addition / subtraction
performance
December-10-14

150
Carry Propagate and Carry Generate

Pi is the carry propagate
Gi is the carry generate
Gi
Ci+1
Pi
Half Adder
(HA)
Half Adder
(HA)
Si
December-10-14
Ai
Bi
Ci

151
Carry Propagate and Carry Generate

Using Pi and Gi, it is possible to rewrite the expressions for the
outputs of the full adder as follows:
Si = Pi Ci
Ci+1 = Gi + PiCi
It is possible to write a Boolean function for each carry
output:
C0 = Input Carry
C1 = G0 + P0C0
C2 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0

December-10-14

152
Carry Lookahead Generator

Using the Boolean function for each carry output, a carry
lookahead generator may be built as follows:
NOTE:
More logic gates are
required to generate
the carry signals but
only two gate delays
are required per carry
signal.
December-10-14

153
4-Bit Carry Lookahead Adder
December-10-14

154
BCD Addition
BCD uses 4-bits to encode each decimal digit
10 bit patterns are valid:
(0000)2, (0001)2, (0010)2, (0011)2, (0100)2,
(0101)2, (0110)2, (0111)2, (1000)2, (1001)2
6 bit patterns are invalid:

(1010)2, (1011)2, (1100)2, (1101)2, (1110)2, (1111)2
When BCD addition results in a carry or an invalid bit pattern,

a value of (0110)2 must be added to the resulting digit to
produce the correct value
Addition of (0110)2 effectively skips the six invalid bit patterns
December-10-14

155
BCD Addition
There are 2 cases to consider:
1. A carry is produced by the binary addition of BCD digits
2. The result of the binary addition of BCD digits is an invalid bit
pattern
Assume that two BCD digits are added using binary addition
resulting in a Carry Out labeled C and a 4-bit value labeled
Z8Z4Z2Z1
An Output Carry (OC) for BCD addition can be expressed as

follows:
OC = C + Z8(Z4)Z2(Z1) + Z8(Z4)Z2Z1 + Z8Z4(Z2)(Z1) + Z8Z4(Z2)Z1 + Z8Z4Z2(Z1) + Z8Z4Z2Z1
OC = C + Z8Z2 + Z8Z4
December-10-14

156
BCD Addition Circuit
NOTE:
If Z8 and Z4 are both
1 or if Z8 and Z2 are
both 1 or if a Carry
Out is generated, the
summation value is
greater than 10. In
any of these cases, a
second addition is
performed to add 6 to
the result to produce
the correct BCD digit.
December-10-14

157
Unsigned Binary Multiplication

Consider two unsigned binary numbers A and B consisting of
two bits each
Assume the multiplier bits are A1A0 and the multiplicand bits are
B1 B 0
Multiplying A and B results in a 4-bit quantity C

The resulting product bits are C3C2C1C0
Multiplication can be accomplished by computing the partial

products
Partial products of two bits are computed using AND gates
Both bits must be 1 for the resulting partial product to be a 1
December-10-14

158
Binary Multiplication
Multiplication can be accomplished by computing the partial
products as follows:
B1
B0
A1
A0
--------A0B1 A0B0
A1B1 A1B0
------------------C3
C2
C1
C0
December-10-14

159
2-Bit by 2-Bit Binary Multiplier Circuit
December-10-14

160
4-Bit by 3-Bit Binary Multiplier Circuit
December-10-14

161
Comments on Multiplication Circuits

The number of adders required grows as the size of the
multiplier grows
For an n-bit multiplier, n - 1 adders are typically required
Advanced multiplier designs exist

Common design tradeoffs include the following:
Hardware complexity vs. performance
Hardware area vs. performance
Hardware cost vs. performance
December-10-14

162
Multiply and Accumulate Circuits

Adders and multipliers are the basis for many complex
devices
Processors and DSPs (Digital Signal Processors) use MAC
(Multiply and Accumulate Circuits) to perform complex
mathematical operations
Application Note
December-10-14

163
Magnitude Comparator
Magnitude comparator is an essential component of a
processor
Comparators enable branching in a computer program
Three important comparisons exist:

1. A > B
2. A < B
3. A = B
Complexity of implementing all three comparisons is not

significantly greater than the complexity of implementing just
one comparison
December-10-14

164
Magnitude Comparator Circuit
NOTE:
x3 indicates that
B3 are equal.
x2 indicates that
B2 are equal.
x1 indicates that
B1 are equal.
x0 indicates that
B0 are equal.
December-10-14
A3 and
A2 and
A1 and
A0 and

165
Decoders
Decoders convert a binary quantity into a high (or low) signal
on a particular output
For example, a 2-to-4-line decoder takes a 2-bit binary
encoded input and drives one of four output lines to a defined
value
Decoders are often used to enable devices on a bus that are
memory-mapped
December-10-14

166
Decoder Example
If a video card memory maps to address 0xA000 in a
computer, a 4-to-16-line decoder can be used to distinguish
address 0xA000 from address 0xB000:
Use the 4 most significant bits as the inputs to the decoder
The 16 output lines will correspond with each of the 16 possible
address ranges
0x0000 to 0x0FFF
0x1000 to 0x1FFF
0xF000 to 0xFFFF
December-10-14

167
3-to-8 Line Decoder
NOTE:
The outputs are active-high.
December-10-14

168
2-to-4-Line Decoder with Enable Input
NOTE:
The outputs are active-low.
December-10-14

169
Building Large Decoders

Large decoders can be constructed using small decoders as
building blocks
A 4-to-16-line decoder can be created using two 3-to-8-line
decoders
One input bit enables one of the two 3-to-8-line decoders
Other three input bits drive the 3-to-8-line decoders
Similarly, a 4-to-16-line decoder can be created using four 2to-4-line decoders
December-10-14

170
Building Larger Decoders
December-10-14

171
Unusual Use of a Decoder
December-10-14

172
Encoders
Encoders perform the inverse operation of a decoder
Encoders look for a signal driven on one of a set of input lines
and drive a binary output based on the position of the signal
In the case of multiple signals driven on the input lines, the

most significant line is given priority
For example, a 4-input priority encoder drives a binary output
based on the most significant input line driven
December-10-14

173
4-Input Priority Encoder

A 4-input priority encoder outputs a binary quantity based on
the most significant input wire driven
The truth table for a 4-input priority encoder is the following:
December-10-14
D3
D2
D1
D0

174
4-Input Priority Encoder Karnaugh Map
NOTE:
These K-Maps differ
slightly from the ones
in the textbook.
Inputs: D3, D2, D1, D0

Outputs: x, y
December-10-14

175
4-Input Priority Encoder Circuit
December-10-14

176
Multiplexers
A multiplexer selects one set of input signals from many sets
of input signals and outputs the chosen set
For example, a 2-to-1-line multiplexer chooses from 2 input
signals and outputs the value that appears on one of them on
the output signal
Multiplexers allow the sharing of a signal wire over time (also
known as time multiplexing)
Multiplexers are used extensively in FPGAs to route signals on

a fixed number of signal wires
December-10-14

177
2-to-1-Line Multiplexer
I0
Y
I1
s
December-10-14

178
4-to-1-Line Multiplexer
I0
I1
I2
I3
s0
s1
December-10-14

179
Quadruple 2-to-1-Line Multiplexer
A
B
4
4
4
S
E
December-10-14

180
Demultiplexers
Demultiplexers (sort of) reverse the process of multiplexing
A decoder with an enable input is a demultiplexer
December-10-14

181

Synchronous Sequential Logic
Sequential Circuits
Sequential circuits introduce state to a digital logic system
State is saved using memory elements
Outputs of a sequential circuit are a function of both inputs
and state
December-10-14

183
Synchronous vs. Asynchronous

Synchronous sequential circuit depends upon the input signals
at discrete instants of time
Easier to build synchronous sequential circuits correctly
Utilizes clocked storage elements to store state
Asynchronous sequential circuit depends upon the input

signals at any instant of time and the order in which the
inputs change
More difficult to build asynchronous sequential circuits correctly
Utilizes time delays to store state temporarily
Effectively a combinational circuit with feedback
December-10-14

184
Clock Signals
Synchronous sequential circuits utilize clock signals to
determine when to evaluate input signals and state
Clock signals can be:
1. Periodic (i.e., fixed frequency)
2. Aperiodic (i.e., variable frequency)
or
December-10-14

185
Clocked Sequential Circuits

Clocked sequential circuits use storage elements called flip-flops
Flip-flop is a clocked circuit that stores a single bit of information
December-10-14

186
Latches
Latches are the simplest form of storage element
Latch is a primitive form of a flip-flop that is sensitive to
changes in the level of input signals
Use cross-coupled NOR or NAND gates to implement storage

Latches are examples of asynchronous sequential circuits
December-10-14

187
SR Latch
SR latch is a set-reset latch
S signal sets the latch to a 1 (assuming that R signal is 0)
R signal sets the latch to a 0 (assuming that S signal is 0)
If both S and R signals are asserted, the latch enters an
unusual state
Both Q and Q signals are set to 0
December-10-14

188
SR Latch
A logic diagram and the truth table for the SR latch are
provided below:
December-10-14

189
SR Latch
Alternatively, the SR latch may be implemented with NAND
gates as follows:
NOTE: This is really a SR latch
NOTE:
Active-low signals
have been used
December-10-14

190
SR Latch with Control Input

A control signal C can be introduced to control the inputs to
the SR latch
C acts as an enable signal or as a clock signal
December-10-14

191
Indeterminate State
The next state of Q is indeterminate when all inputs to the SR
latch with control input are 1
Previously, it could be said that an SR latch would produce 1s at
the output of the SR latch implemented with NAND gates
When the control input is added, it is not clear what the stable
state will be once the control signal C is deasserted
Slight timing differences in the gate delays and propagation
delays might bias the indeterminate state
As long as the indeterminate state is avoided, the circuit is

very useful
December-10-14

192
D Latch
Rather than set or reset a latch, it is more desirable to have
one input, D, that sets the latch to a defined value
D latches can be built using SR latches with control inputs
D latches avoid the indeterminate state
December-10-14

193
D Latch
The D latch can be built as follows:
December-10-14

194
Graphic Symbols for Latches

The graphic symbols for latches are simply boxes with the
inputs labelled as follows:
December-10-14

195
Level-Triggered vs. Edge-Triggered

Changes in the outputs of latches and flip-flops are triggered
by changes in the inputs
Triggers can be any of the following:
High (positive) level of a control signal C
Low (negative) level of a control signal C
Rising (positive) edge response to a control signal C
Falling (negative) edge response to a control signal C
Level-triggered devices update outputs constantly when the

desired control signal is asserted
Edge-triggered devices update outputs immediately after the
desired edge occurs
December-10-14

196
Trigger Response Examples

Examples of level-triggered and edge-triggered responses are
illustrated in the following:
December-10-14

197
Latch and Flip-Flop Terminology

Terminology is not always clear
Some textbooks, manuals, and resources refer to edge-triggered
latches and level-triggered flip-flops
For the purpose of this course:

Latches are level-triggered devices
Flip-flops are edge-triggered devices
December-10-14

198
Comments on Level-Triggering
Level-triggering works well in some applications:
1. If the inputs rarely change during a clock cycle, outputs will
rarely change
2. If the outputs feed flip-flop inputs, changes in the outputs are
irrelevant
Level-triggering works poorly in most applications:

1. If combinational logic is driven by the outputs of a latch, many
intermediate signals (and signal transitions) will be generated
2. If clocked sequential logic is driven by the outputs of a latch,
transitions may occur to close to the rising-edge of the clock
December-10-14

199
Edge-Triggering
How do you produce an edge-triggered device?
ANSWER:
Edge-triggered devices use two latches in series to block
undesirable changes in output signals
This configuration is known as a Master-Slave configuration
NOTE:
The master-slave terminology is now the subject of a
controversy. For more details, check out the following
online article:
http://www.theregister.co.uk/content/28/34216.html
December-10-14

200
Master-Slave D Flip-Flop
Master-slave flip-flops are built using two D latches as
follows:
December-10-14

201
Behaviour of the Master-Slave D Flip-Flop

The master-slave D flip-flop on the previous slide is an
example of a negative-edge-triggered flip-flop
When the CLK signal transitions from a high signal to a low
signal, the value of Q changes
At all other times, changes to the input D are filtered out by the
circuit
It should be noted that since a positive CLK signal is used by

one latch and a negative CLK signal is used by the other latch,
only one latch can update its output at one time
First D latch stores input when CLK is 1
Second D latch stores output of first D latch when CLK is 0
Output of first D latch will not change when second D latch is
active
December-10-14

202
Positive-Edge-Triggered D Flip-Flop
How can a positive-edge-triggered flip-flop be built?
ANSWER:
Inverting the CLK signal prior to use by either latch results in a
positive-edge-triggered flip-flop
Two inverters are used by the modified circuit simply moving
the original inverter will not work
December-10-14

203
Alternative Implementation
Alternatively, a positive-edge-triggered D flip-flop can be built
(more efficiently) using three SR latches as follows:
December-10-14

204
Graphic Symbols for

Edge-Triggered D Flip-Flops
The following graphic symbols are used for edge-triggered D
flip-flops:
NOTE:
The > on the

symbol denotes
a clock signal
December-10-14

205
Alternative Signs of Rising-Edge-Triggered and

Falling-Edge-Triggered Flip-Flops
Rising-edge-triggers are sometimes denoted by the following
graphic beside the clock pin:
Falling-edge-triggers are sometimes denoted by the following

graphic beside the clock pin:
December-10-14

206
JK Flip-Flop
JK flip-flops are analogous to SR latches
J signal sets the flip-flop
K signal resets the flip-flop
If both J and K are 0, then the flip-flip holds its state
If both J and K are 1, then the flip-flop toggles its state
December-10-14

207
JK Flip-Flop Circuit Diagram

A circuit diagram for the JK flip-flop is shown below:
NOTE:
The outputs of the
flip-flop are used to
enable the J and K
inputs to the OR
gate.
December-10-14

208
T Flip-Flop
T stands for toggle
T flip-flops are built by tying both the J and K inputs of a JK
flip-flop to the same input signal T
The following is a simple circuit diagram for the T flip-flop:
December-10-14

209
Alternative T Flip-Flop Implementation

Alternatively, the T flip-flop can be built using a D flip-flop as
follows:
December-10-14

210
Midterm Review of Sequential Logic

Lets review what we have covered with respect to
Synchronous Sequential Logic:
1. Latches and flip-flops are examples of storage elements
2. Storage elements respond to a trigger event by storing a bit of
data
3. A trigger event is the assertion or deassertion of a control signal
4. A latch is a level-triggered storage element
5. A flip-flop is an edge-triggered storage element
6. Storage elements introduce state into the computation of
outputs
7. Modified truth tables called characteristic tables are used to
specify the behaviour of storage elements
December-10-14

211
Review of the D Flip-Flop

The D flip-flop is described by the following characteristic
equation:
Q(t + 1) = D
The characteristic table for the D flip-flop is the following:

D
Q(t + 1)
Description of Operation
Reset
Set
NOTE:
Q(t + 1) denotes the future value of Q at time t + 1
December-10-14

212
Review of the D Flip-Flop

The following timing diagram illustrates the ideal behaviour of
a positive-edge-triggered D flip-flop
D
CLOCK
Inputs
Outputs
Q
Trigger 1
December-10-14
Trigger 2
Trigger 3

213
Accurate Timing for the D Flip-Flop

This is (somewhat) beyond the scope of this course but here
is a more realistic timing diagram for a D flip-flop:
December-10-14

214
D Flip-Flop Implementation
December-10-14

215
Review of the JK Flip-Flop

The JK flip-flop is described by the following characteristic
equation:
Q(t + 1) = JQ(t) + KQ(t)
The characteristic table for the JK flip-flop is the following:
December-10-14
Q(t + 1)
Q(t)
No Change
Reset
Set
Q(t)
Complement

216
Review of the JK Flip-Flop

a positive-edge-triggered JK flip-flop
K
J
CLOCK
Inputs
Outputs
Trigger 1
December-10-14
Trigger 2
Trigger 3

217
JK Flip-Flop Implementation
December-10-14

218
Review of the T Flip-Flop

The T flip-flop is described by the following characteristic
equation:
Q(t + 1) = T Q(t)
The characteristic table for the T flip-flop is the following:
December-10-14
Q(t + 1)
Q(t)
No Change
Q(t)
Complement

219
Review of the T Flip-Flop

a positive-edge-triggered T flip-flop
T
CLOCK
Inputs
Outputs
Q
Trigger 1
December-10-14
Trigger 2
Trigger 3

220
T Flip-Flop Implementations
December-10-14

221

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Department of Electrical and Computer Engineering

Number Systems and Information

Copyright 2005 by W. D. Bishop. All Rights Reserved

Decimal Number System

For fractional quantities, negative exponents are used

Lecture Notes - SE 141: Digital Circuits and Systems

Digital Information Representation

Some binary representations of 0s and 1s are the following:

Voltage (e.g., 3.3 V)

Current (e.g., 0 mA)

Current (e.g., 10 mA)

Switch Position (e.g., closed)

Switch Position (e.g., open)

Capacitor (e.g., discharged)

Capacitor (e.g., charged)

Lecture Notes - SE 141: Digital Circuits and Systems

Binary Number System

This table is similar to

Lecture Notes - SE 141: Digital Circuits and Systems

Decimal Number System

Binary Number System

Digits range from 0 to 9

Digits range from 0 to 1

Fewer digits are required to

Many digits are required to

Decimal vs. Binary Comparison Example

(8 192)10 = (1 0000 0000 0000)2

Lecture Notes - SE 141: Digital Circuits and Systems

220 = 1 048 576

230 = 1 073 741 824

240 = 1 099 511 627 776

Lecture Notes - SE 141: Digital Circuits and Systems

Unsigned Binary Arithmetic

Lecture Notes - SE 141: Digital Circuits and Systems

Unsigned Binary Arithmetic

Lecture Notes - SE 141: Digital Circuits and Systems

Some Conversion Examples

(82.625)10 = (0101 0010.101)2

The last conversion is quite ugly. The conversion algorithm is

Lecture Notes - SE 141: Digital Circuits and Systems

Conversion of (0.0125)10 to Binary

(0.0000 0011 0)2

(0.0000 0011 00)2

Lecture Notes - SE 141: Digital Circuits and Systems

(1010 1011)2 = (253)8 = (171)10

Octal is rarely used

Lecture Notes - SE 141: Digital Circuits and Systems

(1010 1011)2 = (253)8 = (171)10 = (AB)16

Hexadecimal is often used in C, C++, and C# to specify large

Lecture Notes - SE 141: Digital Circuits and Systems

Lecture Notes - SE 141: Digital Circuits and Systems

Diminished Radix Complement

For the binary number system, the diminished radix

Lecture Notes - SE 141: Digital Circuits and Systems

For the binary number system, the radix complement is

Lecture Notes - SE 141: Digital Circuits and Systems

Subtraction with rs Complement

Lecture Notes - SE 141: Digital Circuits and Systems

= M + 2s complement of N (sort of)

Lecture Notes - SE 141: Digital Circuits and Systems

= M + 2s complement of N (sort of)

Lecture Notes - SE 141: Digital Circuits and Systems

Subtraction with (r - 1)s Complement

Lecture Notes - SE 141: Digital Circuits and Systems