VLSI Physical Design Automation

Lecture 2. Review of Device/VLSI/Algorithm

Prof. David Pan
dpan@ece.utexas.edu
Office: ACES 5.434

12/16/2014

Objective of this Lecture

To review the materials used in fabrication of VLSI
devices.
To review the structure of devices and process
involved in fabricating different types of VLSI circuits
To review the basic algorithm concepts

To level-set everyone so that we can get into serious

Physical Design topics in the next lecture

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Wafer, Die and Package

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Fabrication Materials

copper

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Electron and Holes

Silicon
atom

Free
Electron

+Ion

Hole

http://researchweb.watson.ibm.com/resources/press/strainedsilicon/

Holes travel as do electrons

Material can be enriched in holes or electrons by introducing impurities
Holes in crystals can be enriched by embedding some boron atoms
Electrons in crystals can be enriched by embedding phosphorus atoms
Recent breakthroughs: strained silicon (IBM) to stretch silicon such that
electrons experience less resistance and flow up to 70% faster
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The Three Regions in a n-p Junction

Carrier-depletion
zone

Electron
rich

Interface Hole rich

Formation of a Diffused Junction

Mask

Silicon dioxide
insulator
Phosphorous

Depletion
zone

(a)

(b)

Substrate

(c)

A mask is a specification of geometric shapes that need to

be created on a certain layer. Masks are used to create a
specific patterns of each material in a sequential manner
and create a complex pattern of several layers
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A nMOS Transistor
Enhancement Mode
Source

Gate

Drain

(a)

Channel

Source

Drain

VgVt

Vg<Vt

Vs

(b)

Gate

Vd Vs

Vd

(c)

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Fabrication of VLSI Circuits

1. Create
2. Define
3. Etch

Silicon wafers

Material formation by deposition,

diffusion or implantation

Pattern definition by
photolithography

Etch
8 to 10 iterations

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Photolithographic Process
UV Radiation
Silicon dioxide
Photoresist (Negative )
Silicon

Photo mask with

opaque feature

Shadow of
mask feature
(a)

(b)

Hardened
Photoresist

(c)

(d)
Photoresist
stripped

Silicon dioxide
etched where
exposed

(e)

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Details of Fabrication Processes

Crystal growth & wafer preparation
Epitaxy
Dielectric & polysilicon film deposition
Oxidation

Diffusion
Ion implantation
Lithography
Etching
Packaging

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Basic Design Rules

1. Size Rules
2. Separation Rules
3. Overlap Rules
Basic nMOS Design Rules
Diffusion Region Width
Polysilicon Region Width
Diffusion-Diffusion Spacing
Poly-Poly Spacing
Polysilicon Gate Extension
Contact Extension
Metal Width

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2
2
3
2
2

11

Size and Separation Rules

Diffusion

Poly

Metal

Incorrectly and Correctly Formed Channels

Diffusion
Short

Channel

Poly

Incorrectly formed

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Correctly formed

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Overlap Rules for Contact cuts

(b)

(a)

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Layout of Basic Devices

nMOS Inverter
CMOS Inverter
nMOS NAND Gate
CMOS NAND Gate
nMOS NOR Gate
CMOS NOR Gate
Complicated devices are constructed by using basic devices

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A CMOS Inverter

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A CMOS NAND Gate

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A CMOS NOR Gate

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Additional Fabrication Factors

Scaling
Parasitic Effects
Yield Statistics and Fabrication Costs

Delay Computation
Noise and Crosstalk
Power Dissipation

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Mini Summary
The three types of materials are insulators, conductors and
semiconductors

A VLSI chip consists of several layers of different materials on

a silicon wafer.
Each layer is defined by a mask
VLSI fabrication process patterns each layer using a mask

Complex VLSI circuits can be developed using basic VLSI

devices
Design rules must be followed to allow proper fabrication
Several factors such as scaling, parasitic effects, yield
statistics and fabrication costs, delay computation, noise and
crosstalk and power dissipation play a key role in fabrication
of VLSI chips

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Design Styles
Complexity of
VLSI circuits
Performance

Size

Cost

Market time

Different design styles

Full custom

Standard Cell

Gate Array

FPGA

Cost, Flexibility, Performance

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Full Custom Design Style

Pad

Metal

Via

Data Path
PLA

Metal 2

I/O

ROM/RAM

Random logic

A/D Converter

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Standard Cell Design Style

Cell
Feedthrough
VDD Metal 1
GND
Metal 2

Cell A
Cell C

Cell B

Cell D

Feedthrough cell

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Gate Array Design Style

A
C
B
VDD

Metal1 Metal2

C
A

Structured ASICs (hot topics nowadays) are essentially gate array

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FPGA Design Style

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Field-Programmable Gate-Arrays (FPGAs)

Programmable logic
Programmable interconnects
Programmable inputs/outputs

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Comparisons of Design Styles

style
full-custom standard cell gate array

FPGA

cell size

variable

fixed height *

fixed

fixed

cell type

variable

variable

fixed

programmable

cell placement

variable

in row

fixed

fixed

interconnections

variable

variable

variable

programmable

* uneven height cells are also used

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Comparisons of Design Styles

style
full-custom standard cell
compact

gate array

FPGA

moderate

large

Area

compact

Performance

high

high
to moderate

moderate

low

Fabrication
layers

ALL

ALL

routing
layers

none

to moderate

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Packaging Styles
Packaging

Printed Circuit Board

PCB

Multi-Chip Module
MCM

Wafer Scale Integration

WSI (SOC)

Area
Performance, cost

The increasing complexity and density of the semiconductor devices

are driving the development of more advanced VLSI packaging and
interconnection approaches.

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History of VLSI Layout Tools

Year
1950 - 1965

Design Tools
Manual Design

1965 - 1975

Layout editors
Automatic routers( for PCB)
Efficient partitioning algorithm

1975 - 1985

Automatic placement tools

Well Defined phases of design of circuits
Significant theoretical development in all phases

1985 1995

Performance driven placement and routing tools

Parallel algorithms for physical design
Significant development in underlying graph theory
Combinatorial optimization problems for layout

1995 2002

Interconnect layout optimization, Interconnectcentric design, physical-logical codesign

2002 - present

Physical synthesis with more vertical integration

for design closure (timing, noise, power, P/G/clock,
manufacturability)

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Now You Need Algorithms

To put devices/interconnects together into VLSI chips
Fundamental questions: How do you do it smartly?
Definition of algorithm in a board sense: A step-bystep procedure for solving a problem. Examples:
Cooking a dish
Making a phone call
Sorting a hand of cards

Definition for computational problem: A well-defined

computational procedure that takes some value as
input and produces some value as output

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Example: Selection Sort

Input: An array of n numbers D[1]D[n].
Output: An array of n numbers E[1]E[n] such that
E[1]E[2] E[n].
Algorithm:
1. For i from 1 to n do
2.
Select the largest remaining no. from D[1..n].
3.
Put that number into E[i].

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Some Algorithm Design Techniques

Greedy
Divide and Conquer
Dynamic Programming
Network Flow
Mathematical Programming (e.g., linear programming,
integer linear programming)

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Reduction
Idea: If I can solve problem A, and if problem B can be
transformed into an instance of problem A, then I can
solve problem B by reducing problem B to problem A
and then solve the corresponding problem A.
Example:
Problem A: Sorting
Problem B: Given n numbers, find the i-th largest numbers.

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Analysis of Algorithm
There can be many different algorithms to solve the
same problem.
Need some way to compare 2 algorithms.
Usually run time is the most important criterion used
Space (memory) usage is of less concern now

However, difficult to compare since algorithms may be

implemented in different machines, use different
languages, etc.
Also, run time is input-dependent. Which input to use?
Big-O notation is widely used for asymptotic analysis

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Big-O Notation
Consider run time for the worst input
=> upper bound on run time.
Express run time as a function input size n.
Interested in the run time for large inputs.
Therefore, interested in the growth rate.
Ignore multiplicative constant.
Ignore lower order terms.
3n2+6n+2.7 is O(n2).
n1.1+10000000000n is O(n1.1).
n1.1 is also O(n2), but to be more precise, it is O(n1.1)

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Effect of Multiplicative Constant

800

n2

700
Run time

600
500
400

10n

300
200
100
0
0

10
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n
36

Growth Rates of some Functions

n O n

O n log n O n log 2 n O n1.5 O n 2

O n O n
3

O 2
O 2 O 3 O 4
O n! O n
O n

log2 n

log n

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Exponential
Functions

O n c O 2 c logn for any constant c

Polynomial
Functions

O log n O log 2 n O

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Problem of Exponential Function

Consider 2n, value doubled when n is increased by 1.
n

2n

1ms x 2n

10

103

0.001 s

20

106

1s

30

109

16.7 mins

40

1012

11.6 days

50

1015

31.7 years

60

1018

31710 years

If you borrow $10 from a credit card with APR 18%, after
40 yrs, you will own $12700!
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NP-Complete
The class NP-Complete is the set of problems which
we believe there is no polynomial time algorithms.
Therefore, it is a class of hard problems.
NP-Hard is another class of problems containing the
class NP-Complete.
If we know a problem is in NP-Complete or NP-Hard,
there is no hope to solve it efficiently.

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NP-Complete
I can't find an efficient
algorithm, I guess I'm just too
dumb.

I can't find an efficient

algorithm, but neither can all
these famous people.

I can't find an efficient

algorithm, because no such
algorithm is possible.

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Source: Computers and Intractibility by Garey and Johnson

Solution Type of Algorithms

Polynomial time algorithms

Exponential time algorithms
Special case algorithms
Approximate algorithms
Heuristic algorithms

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Before Next Class

Refresh your Algorithms:
C. J. Alpert, D. P. Mehta, S. S. Sapatnekar, Handbook of
Algorithms for Physical Design Automation, Auerbach
Publications, 2008
T. H. Cormen, C. E. Leiserson, R. L. Rivest, C. Stein
Introduction to Algorithms, MIT Press, 2009 (3rd edition)

Circuit partitioning in the next class

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