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Chris Erickson
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Graduate
Student
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
Chris.Erickson@auburn.edu
Objectives
Why SATA was invented
What is PATA?
All of the below synonyms refer to a modern day
PATA drive
PATA Parallel Advanced Technology Attachment
UDMA Ultra Direct Memory Access
IDE Integrated Device Electronics
EIDE Enhanced IDE
More on PATA
40 & 80 wire cable option
40 wire limited to UDMA 33 MB/s and below
80 wire allowed for UDMA 66, 100, 133 MB/s
SATA Basics
New Connector
Saves space
More reliable
More air flow
SATA Basics
SATA I for 1.5Gbps ~ 150MB/s
Connectivity
Serial ATA is point-to-point topology
Hosts can support multiple devices but
requires multiple links
100% available link bandwidth
Failure of one device or link does not affect
other links
Link Characteristics
SATA uses full-duplex links
Protocol only permits frame transfer in one
direction at a time
Each link consists of a transmit and a receive
pair
Power Management
SATA has
Phy Ready Capable of sending and receiving data.
Main phase locked loop are on and active
Partial Physical layer is powered but in a reduced
state. Must be able to return to Phy Ready within 10
us.
Slumber Physical layer is powered but in a reduced
state. Must be able to return to Phy Ready within 10
ms.
Application
DMA management
DMA management
Buffer Memory
Transport
Link
Host Layers
Physical
Device Layers
Physical Layer
Transmission (Tx) and Reception (Rx) of a
1.5Gb/s serial stream
Perform power on sequencing
Perform speed negotiation
Provide status to link layer
Support power management requests
Out-of-Band (OOB) signal generation and
detection
Out of Band
Part of normal power on sequence
COMINIT
Always originated by the device
Requests a link reset
Issued by device in response to COMRESET
320 ns
106.7 ns
COMWAKE
106.7 ns
106.7 ns
Host
Device
Data In
Tx -
Serializer
Align Generator
Tx Clock
Phy Reset
Phy Ready
Slumber
Partial
SPD Select
SPD Mode
System Clock
Port Control
Logic
Rx +
Data Out
RX Clock
COMRESET /
COMINIT
COMWAKE
Deserializer
Rx OOB Detect
Application
DMA management
DMA management
Buffer Memory
Transport
Link
Host Layers
Physical
Device Layers
Link Layer
8b / 10b encoding
Scrambles and descrambles data and
control words
Converts data from transport layer into
frames
Conduct CRC generation and checking
Provides frame flow control
Encoding Concepts
All 32 bit Dwords are encoded for SATA
32 bits data = 40 bits of transmission
0 0 1 1 1 1 1 1
This 10b Character transmitted
when CRD negative
1 0 1 0 1 1 1 0 0 1
0 1 0 1 0 0 1 0 0 1
This character
This character
6 ones
4 ones
4 zeros
6 zeros
Disparity +2
Disparity -2
SATA Primitives
Convey real-time state information
SATA Primitives
ALIGN Speed negotiation and at least
every 256 Dword
SYNC Used when in idle to maintain bit
synchronization
CONT Used to suppress repeated
primitives
SATA Primitives
X_RDY
SOF
R_RDY
EOF
R_IP
R_OK
R_ERR
HOLD
HOLDA
SOF
Payload Data
CRC
EOF
SYNC
SYNC
SYNC
SYNC
Host
SYNC
SYNC
Device
SYNC
SYNC
SYNC
SYNC
SYNC
X_RDY
X_RDY
X_RDY
SYNC
Host
SYNC
SYNC
Device
SYNC
SYNC
SYNC
SYNC
SYNC
X_RDY
X_RDY
X_RDY
X_RDY
Host
SYNC
X_RDY
Device
SYNC
R_RDY
R_RDY
R_RDY
R_RDY
DATA
DATA
SOF
X_RDY
Host
R_RDY
X_RDY
Device
R_RDY
R_RDY
R_RDY
R_RDY
R_RDY
DATA
DATA
DATA
DATA
Host
R_RDY
DATA
Device
R_RDY
R_IP
R_IP
R_IP
R_IP
WTRM
EOF
CRC
DATA
Host
R_IP
DATA
Device
R_IP
R_IP
R_IP
R_IP
R_IP
WTRM
WTRM
WTRM
EOF
Host
R_IP
CRC
Device
R_IP
R_IP
R_IP
R_IP
R_IP
WTRM
WTRM
WTRM
WTRM
Host
R_IP
WTRM
Device
R_IP
R_OK
R_OK
R_OK
R_OK
SYNC
SYNC
SYNC
WTRM
Host
R_OK
WTRM
Device
R_OK
R_OK
R_OK
R_OK
R_OK
SYNC
SYNC
SYNC
SYNC
Host
R_OK
SYNC
Device
R_OK
SYNC
SYNC
SYNC
SYNC
Application
DMA management
DMA management
Buffer Memory
Transport
Link
Host Layers
Physical
Device Layers
Transport Layer
Responsible for the management of
Frame Information Structures (FIS)
At the command of Application layer:
Format the FIS
Make frame transmission request to Link layer
Pass FIS contents to Link layer
Receive transmission status from Link layer
and reports to Application layer
FIS types
FIS TYPE
CODE
27h
34h
A1h
39h
41h
58h
5Fh
46h
Description
Direction
PIO Setup
Data
D
D
D
D
D
D
H
H
H
H
H
H
H
Features
Byte 2
Byte 1
Command Reserved
Byte 0
FIS TYPE
(27h)
Dword 1 Dev/Head
Cyl High
Cyl Low
Sector
Number
Dword 2
Features
(exp)
Cyl High
(exp)
Cyl Low
(exp)
Sector
Number
Dword 3
Control
Reserved
Sector
Count
Sector
Count
Byte 2
Byte 1
Byte 0
Reserved
[ TASLFPRV ]
Reserved
Data [15:8]
Data [7:0]
Data [15:8]
Data [7:0]
Data FIS
Byte 3
Byte 2
Byte 1
Byte 0
Dword 1
Dword 2
...
Dword N
N Dwords of Data
Minimum 1 Dword
Maximum 2048 Dwords
Application
DMA management
DMA management
Buffer Memory
Transport
Link
Host Layers
Physical
Device Layers
Completed !!
Any Question? Comments?