Interrupts in MCU

(dsPic30f4011)

Group 3: Hoang Anh Tuan

Truong Thanh Tung
Nguyen Van Quan
Ngo Van Oanh

Lecturer : Vo Duy Thanh

Content
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Introduce to interrupts
Interrupts in ds PIC
Interrupts Priority
Reset Sequence
Traps
Interrupts Sequence
Alternate Interrupt Vector Table
External Interrupt Requests
Fast Context Saving
Interrupts Nesting
Wake-up from Sleep and Idle
Homework
Reference Manual.

1. Introduce to interrupts
<? >What is an interrupt?
An interrupt is a little piece of hardware that sits,
waiting to detect a trigger event, such as a particular pin
going from a low state to a high state.

When this event happens:

1. the interrupt triggers
2. the microcontroller stops executing it's current program
3. the microcontroller starts executing an Interrupt Service
Routine, or ISR
4. when the ISR is done, we return to the original program

 In your ISR, you would have code that does some

processing to handle the event. For instance, your ISR
would:
- Increment the value of a counter, if you were counting
pulses from an encoder
- Stop the robot if you were using interrupt bumpers
Most microcontrollers support a wide variety of
interrupt triggers:
-A particular pin state going from low to high
- A particular pin state going from high to low
- Any change on a particular pin

2. Interrupts in (ds)PIC
The dsPIC30f4011/4012 has 30 interrupt sources and 4
processor exceptions
Interrupt Source : External Interrupt, Input Capture, Output
Compare, Timer , UART Receiver ( transmitter ) , ADC
Convert Done, I2C , SPI, Combined IRQ for CAN, FLTA
PWM Fault A
Special Function Registers
- IFSx ( 3 registers )
- IECx ( 3 registers )
- IPCx ( 12 registers )
- IPLx ( 1 registers)
- INTCONx ( 2 registers )

3. Interrupts priority
Interrupt Piority bits for each individual interrupt
source are located 3 bits of each nibble within the IPCx
register
Natural Order Priority
- determined by the position of an interrupt in the
vector table
- only affects interrupt operation when multiple
interrupts with the same user-assigned priority become
pending at the same time.
Note: the user can assign a very high overall priority level
to an interrupt with a low natural order priority

4. Reset Sequence
A Reset is not a true exception
Reset sources : 5 sources of error caused a
device reset
- Watchdog Time-out
- Uninitialized W Register Trap
- Illegal Instruction Trap
- Brown-out Reset (BOR)
- Brown-out Reset (BOR)

5. Traps
non-maskable interrupts
8 fixed priority levels for
traps, Level 8 through
Level 15

Trap sources :
- Math Error Trap(level 11)
- Address Error Trap(level 13)
- Stack Error Trap(level12)
- Oscillator Fail Trap(level 14)

 Hard and soft trap:

- multiple traps can become active within the same
cycle ( arithmetic error trap )
- Soft traps include exceptions of priority level 8
through level 11. (address error , stack error and
oscillator error )
- Hard traps include exceptions of priority level 12
through level 15.
- Each hard trap that occurs must be acknowledged
before code execution of anytype may continue.
- The device is automatically Reset in a hard trap
conflict condition

6. Interrupt Sequence
All interrupt event flags are sampled in the
beginning of each instruction cycle by the
IFSx registers
The Interrup request ( IRQ ) will cause an
interrupt to occur if the corresponding bit in
the interrupt enable (IECx) register is set

 If there is a pending IRQ with a user assigned

priority level greater than the current processor
priority level, an interrupt will be presented to the
processor .
- the current PC value
- the low byte of the Processor Status register
- the IPL3 status bit
* The RETFIE (return from interrupt) instruction
will unstack the program counter and STATUS
registers to return the processor to its state prior to
the interrupt
sequence

 Note :
- The user can always lower the priority level by
writing a new value into SR. The Interrupt
Service Routine must clear the interrupt flag bits
in the IFSx register before lowering the processor
interrupt priority in order to avoid recursive
interrupts.
- The IPL3 bit is always clear when interrupts are
being processed. It is set only during execution of
traps.

7. Alternate Interrupt Vector Table

Interrupt Vector Table
The IVT resides in program memory, starting at location
0x000004.
- The IVT contains 62 vectors consisting of 8 nonmaskable trap vectors plus up to 54 sources of interrupt.
- In general, each interrupt source has its own vector.
- Each interrupt vector contains a 24-bit wide address.
- The value programmed into each interrupt vector
location is the starting address of the associated
Interrupt Service Routine (ISR).

 Alternate Vector Table

- If the ALTIVT( Enable Alternate Interrupt Vector

Table) bit is set, all interrupt and exception processes
will use the alternate vectors instead of the default
vectors.
- The alternate vectors are organized in the same manner
as the default vectors.
- The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the
interrupt vectors to be reprogrammed.
- If the AIVT is not needed, , the program memory
allocated to the AIVT may be used for other purposes.
- AIVT may be freely programmed by the user

8. External Interrupt Requests

Each external interrupt pin may be programmed
to interrupt the CPU on a rising edge or falling
edge event.
Ex : INT0EP: External Interrupt #0 Edge
Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
to accept external interrupt, source
corresponding(INT0-INT4) is set 1 and GIE
is set 1( bit 15 in INCON1)

9. Fast Context Saving

A context saving option is available using
shadow registers
Shadow registers are provided for the DC,
N,OV, Z and C bits in SR, and the registers W0
through W3

 The shadow registers are accessible using the

PUSH.S and POP.S instructions only.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the
current value of the aforementioned registers
into their respective shadow registers.

 If an ISR of a certain priority uses the PUSH.S

and POP.S instructions for fast context saving,
then a higher priority ISR should not include
the same instructions.Users must save the key
registers in software during a lower priority
interrupt, if the higher priority ISR uses fast
context saving.

10. Interrupt Nesting

Interrupts, by default, are nestable
Any ISR that is in progress may be interrupted by
another source of interrupt with a higher user
assigned priority level.
Interrupt nesting may be optionally disabled by
setting the NSTDIS control bit (INTCON1<15>)
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
The IPL<2:0> bits become read only when
interrupt nesting is disabled. This prevents the
user software from setting IPL<2:0> to a lower
value, which would effectively re-enable interrupt
nesting.

11. Wake-up from Sleep and Idle

The interrupt controller may be used to wake-up
the processor from either Sleep or Idle modes if
Sleep or Idle modes are active when the interrupt
is generated.

12. Interrupt Control and Status Registers

INTCON1, INTCON2 Registers
Global interrupt control functions are derived from
these two registers. INTCON1 contains the Interrupt
Nesting Disable (NSTDIS) bit, as well as the control
and status flags for the processor trap sources. The
INTCON2 register controls the external interrupt
request signal behavior and the use of the alternate
vector table.

INTCON1 Register

o
o
o
o
o
o
o
o
o

bit 15 NSTDIS: Interrupt Nesting Disable bit

bit 10 OVATE: Accumulator A Overflow Trap Enable bit
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit
bit 8 COVTE: Catastrophic Overflow Trap Enable bit
bit 4 MATHERR: Arithmetic Error Status bit
bit 3 ADDRERR: Address Error Trap Status bit
bit 2 STKERR: Stack Error Trap Status bit
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
Others bit : Read as 0

INTCON2 register

bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

bit 14 DISI: DISI Instruction Status bit
bit 13-5 Unimplemented: Read as 0
bit x INTxEP: External Interrupt #x Edge Detect Polarity
Select bit

 IFSx: Interrupt Flag Status Registers

All interrupt request flags are maintained in the IFSx
registers, where x denotes the register number. Each
source of interrupt has a Status bit, which is set by the
respective peripherals or external signal and is cleared via
software.
An example for IFS0, Others IFS registers completely similar.

IFS0 Register

 bit 15 CNIF: Input Change Notification Flag Status bit

bit 14 MI2CIF: I2C Bus Collision Flag Status bit
bit 13 SI2CIF: I2C Transfer Complete Interrupt Flag
Status bit
bit 12 NVMIF: Non-Volatile Memory Write Complete
Interrupt Flag Status bit
bit 11 ADIF: A/D Conversion Complete Interrupt Flag
Status bitbit 10
bit 10 U1TXIF: UART1 Transmitter Interrupt Flag
Status bit
bit 9 U1RXIF: UART1 Receiver Interrupt Flag Status
bit

bit 8 SPI1IF: SPI1 Interrupt Flag Status bit

bit 7 T3IF: Timer3 Interrupt Flag Status bit
bit 6 T2IF: Timer2 Interrupt Flag Status bit
bit 5 OC2IF: Output Compare Channel 2 Interrupt Flag
Status bit
bit 4 IC2IF: Input Capture Channel 2 Interrupt Flag
Status bit
bit 3 T1IF: Timer1 Interrupt Flag Status bit
bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag
Status bit
bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag
Status bit
bit 0 INT0IF: External Interrupt 0 Flag Status bit

 IECx: Interrupt Enable Control Registers

All Interrupt Enable Control bits are maintained in
the IECx registers, where x denotes the register
number. These control bits are used to individually
enable interrupts from the peripherals or external
signals.
An example for IEC0. Others IEC registers
completely similar.

 bit 15 CNIE: Input Change Notification Interrupt

Enable bit
bit 14 MI2CIE: I2C Bus Collision Interrupt Enable
bit
bit 13 SI2CIE: I2C Transfer Complete Interrupt
Enable bit
bit 12 NVMIE: Non-Volatile Memory Write
Complete Interrupt Enable bit
bit 11 ADIE: A/D Conversion Complete Interrupt
Enable bit
bit 10 U1TXIE: UART1 Transmitter Interrupt
Enable bit
bit 9 U1RXIE: UART1 Receiver Interrupt Enable
bit
bit 8 SPI1IE: SPI1 Interrupt Enable bit

 bit 7 T3IE: Timer3 Interrupt Enable bit

bit 6 T2IE: Timer2 Interrupt Enable bit
bit 5 OC2IE: Output Compare Channel 2
Interrupt Enable bit
bit 4 IC2IE: Input Capture Channel 2 Interrupt
Enable bit
bit 3 T1IE: Timer1 Interrupt Enable bit
bit 2 OC1IE: Output Compare Channel 1
Interrupt Enable bit
bit 1 IC1IE: Input Capture Channel 1 Interrupt
Enable bit
bit 0 INT0IE: External Interrupt 0 Enable bit

 IPCx: Interrupt Priority Control Registers

Each user interrupt source can be assigned to one of
eight priority levels. The IPC registers are used to
set the interrupt priority level for each source of
interrupt.
An example for IPC0. Others IPC registers
completely similar.

IPC0 Register

 bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits

bit 10-8 OC1IP<2:0>: Output Compare Channel 1
Interrupt Priority bits
bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt
Priority bits
bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
.
.
.
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Others bit read as 0

 SR: CPU Status Register

The SR is not specifically part of the interrupt controller
hardware, but it contains the IPL<2:0> Status bits
(SR<7:5>) that indicate the current CPU priority level.
The user may change the current CPU priority level by
writing to the IPL bits.
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status
bits

 CORCON: Core Control Register

The CORCON is not specifically part of the interrupt
controller hardware, but it contains the IPL3 Status bit
which indicates the current CPU priority level. IPL3 is a
Read Only bit so that trap events cannot be masked by
the user software.

13. Excersies
1. Vit chng trnh
Vit chng trnh khi to 2 ngt:
; -Ngt ngoi 0 vi u tin cao.
; -Ngt timer 0 vi u tin thp.
; -Ngt INT0 : bt 3 led n RB1, RB2, RB3 sng cng ;lc
; -Ngt timer0 : tt 3 led n RB1, RB2, RB3 sau 1s hin th
k t ln LCD.
2. Chng trnh to xung vung c chu k T=0.01 giy,
rng 50%, s dng thch anh tn s 4Mhz:
3. Chng trnh m xung ngoi a ti chn RB0 (chn ngt
ngoi) hin th s m t 0-99 trn cc led n ni vi
PORTC.

14. Reference Manual

1. Microchip - dsPIC30F4011/4012 Data Sheet High
Performance Digital Signal Controllers.
2. Microchip - dsPIC30F Family Reference Manual HighPerformance Digital Signal Controllers
3. Microchip dsPIC30f Programer s Reference Manual
High-Performance Digital Signal Controllers.

Thank for listening!