Low Power Dissipation &

High Fault Coverage

BIST Pattern Generator
Prepared By:
PARTH SHAH
131060752026
GTU PG SCHOOL

AGENDA
Introduction
> BIST (Built In Self Test)
> Types of Faults
> TPG (Test Pattern Generator)
Architecture of Different TPG
> LT-RTPG (Low Transition Random TPG)
> A-3WRTPG (Arithmetic 3-Weighted Random TPG)
Comparison of
> Fault Covered
> Power Consumption
> Gate Count
Conclusion
References

INTRODUCTION
What is BIST?
Built In Self Test
Concept of Buit In Test + Self Test
Why BIST
Todays Test Requirement for SoC Complexity
Detect un-modeled Faults
Provide Remote Diagnosis

BIST WORKING

Test
Test
Controller

Hardware
Pattern
Generator
Primary
Input

Input
Mux

Circuit Under Test

(CUT)
With optional
modification

Output
Response
Comparator

Primary
Output
Figure 1: BIST Block Diagram

FAULT TYPES
LFSR
Easy To
Detect

More
Transition
Conventional
LFSR

LT-RTPG

FAULT
TYPES

2x1 MUX

Random
Pattern
Resistance

A-3WRTPG

Figure 2 : Fault Types

Modified
form of
Weighted
TPG

TEST PATTERN GENRATOR

Techniques available for TPG
Ad-Hoc Circuitry
Large Circuit should be partitioned into smaller sub-circuits.
Manual Test Access Point still Required.
Asynchronous logic feedback must be avoided.

LFSR
Reduce Correlation between successive test vectors
Most popular due to compact and simple structure

TEST PATTERN GERATOR

Cellular Automata
The CA are very similar to the LFSRs except that the
registers in CA have a logical relationship with their
neighbors only.

BILBO
Selection of TPG based on Fault Types

Different Methods for LT-RTPG

1. Running Test at slower Frequency.

Easy to Implement.
Increase Test Application Time.
Fails to reduce peak power.

2. Scain Chain Ordering

Reduce average power consumption during scan in and scan out

Fails to reduce peak capture power during testing

3. X-filling Technique

Assign values to the dont care bits of a deterministic set of test

vectors.

LT-RTPG
Less Hardware
T FF holds Previous Value until
Input is 1
Output of AND Gate will be 1
for every 15 pattern generated by
BS-LFSR
The Adjacent scan flip flops are
assigned identical values in most
test patterns
so scan input have fewer
transition during scan shift
operation.

Figure 3: Architecture Of Low Transition

Random Test Pattern Generator

BS-LFSR
Generates same no of 1s
and 0s at multiplexers after
swapping of two adjacent
cells.
Output of Mux depends
on three different cells of
LFSR.

Figure 4: Architecture of Bit Swapping Linear

Feedback Shift Register

A 3-WRTPG
Weights are altered in
range of 0 to 1.
3 weights are assigned.
Utilization of adder
modules reduce Hardware
overhead.
Values can be based on
three different condition of
Set and Reset.
Figure 5: Architecture of Arithmetic 3Weighted Random Test Pattern Generator

FULL ADDER TRUTH TABLE

# Cin

A[i] B[i]

S[i]

Cout Comment

Configuration 1:
Set[i] = 1 & Reset[i] = 0 hence
A[i] = 1 & B[i] = 0 Cout = 1 = Cin

Cout = Cin
Cout = Cin

Cout = Cin

Cout = Cin

Configuration 2:
Set[i] = 0 & Reset[i] = 1 hence
A[i] = 0 & B[i] = 1 Cout = 0 = Cin
Configuration 3:
Set[i] = 0 & Reset[i] = 0 hence
A[i] = - & B[i] = 1/0 Depending on
value that will be added to the
accumulator input in order to produce
suitable random pattern to input of
CUT.

PROPOSED ARCHITECTURE

RESULT COMPARISON
We will compare Simulation Result, Power Analysis and

Synthesis result of all the Architecture.

Simulation Result were obtained from modelsim 6.5 by setting
clock frequency 10MHz.
Synthesis Result were obtained from Xilinx 8.2 version.

10 Faults: 4 Easy to Detect & 6 Random Pattern Resistance

PATTERN GENERATED

EASY TO DETECT FAULT

Only 3 Faults
Detected by
simple LFSR
LT-RTPG USING LFSR

Fault Coverage is Improved to 15%

LT-RTPG USING BS-LFSR

4 Easy to
Detect Faults
Detected by
BS-LFSR

TOTAL FAULTS COVERED

SIMPLE BIST TPG

Using Simple
BIST TPG total
6 Faults are
Detected

Fault Coverage is Improved to 25%

PROPOSED BIST TPG

With Proposed
BIST we can
detect all 9 Faults
are Detected

POWER ANALYSIS
LT-RTPG
Using
LFSR

LT-RTPG Arithmetic
Using
BIST
BS-LFSR

BIST
TPG[1]

Proposed
BIST TPG

Total
Quiescent
Power

0.025

0.025

0.025

0.025

0.025

Total
Dynamic
Power

0.062

0.039

0.050

0.159

0.123

Total
Power

0.086

0.063

0.074

0.183

0.148

As seen from above table there is a reduction in

power consumption when used BS-LFSR instead of
LFSR

GATE COUNT ESTIMATION

BIST TPG

Proposed BIST TPG

Number of GCLKs

Number of GCLKIOBs

Total Equivalent Gate Count

for Design

324

300

Additional JTAG gate count for

IOBs

912

528

So we can say that Proposed BIST occupied

considerably less area than that of BIST TPG.

CONCLUSION
With Proposed BIST TPG
Power Consumption is 15% reduced
Fault Coverage almost 100%
Area Occupied is 40% reduced

REFERENCES
1) Seongmoon Wang, A BIST TPG for low power dissipation and high fault
coverage, IEEE transaction on VLSI systems vol.15, no.7, july 2007
2) Abdallatif S abu-issa and Steven F. Quigley, Bit-Swapping and scan chain
ordering: A Novel technique for peak and average power reduction in
scan based BIST, IEEE transactions on computer aided design of
integrated circuits and systems, Vol.28, No.5, May 2009
3) Chand SR, Srinivas.V, Sai T.V., Sailaja.M, and Madhu.J., Fault diagnosis
using TPG low power dissipation and fault coverage ,Published in
Computational intelligence and computing research (ICCIC), 2010 IEEE
international conference.
4) M. Chatterjee and D. K. Pradhan, A new pattern biasing technique for
BIST, in Proc. VLSITS, 1995, pp. 417425.