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VHDL Syntax 1
Outline
What is VHDL
VHDL Syntax
VHDL Program Structure
Entity
Architecture
Concurrent and Sequential Statements
What is VHDL
VHDL: Very High Speed Integrated Circuits
Hardware Description Language
Originally developed as a standard mean to document complex
circuits
Later for ASIC design to Printed Circuit Board (PCB) system
What is VHDL
VHDL allows design re-use by taking deviceindependent VHDL codes as component
High portability:
Same code can be implemented on different logic devices
Statements termination: ;
List delimiter: ,
Signal assignment: <=
Signal comparsion:
= to compare if they are equal
/= to compare if they are different
Entity
Entity
Data types:
std_logic, std_logic_vector, bit, integer
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Architecture
Architecture
The behaviour and function of an entity
Many different ways to describe the same design
For example:
Concurrent / dataflow
Sequential
Structural (Will be covered in next tutorial)
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Architecture Example 1
A dataflow description:
Concurrent
statement
Concurrent statements:
Order of the statements is not important
All statements have effects simultaneously
Example:
Boolean equations
With-select-when statements
When-else statements
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Architecture Example 2
A sequential description:
Concurrent
statement
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2-to-1 MUX
When S = 0
Y=A
When S = 1
Y=B
2-to-1 MUX
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2-to-1 MUX
LIBRARY statement is used to reference a group of
previously defined VHDL design units or packages
USE statement specifies what entities or packages to
use in this libray
STD_LOGIC_1164 package defines a multi-valued
logic system which will be used as data types for the
signals
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2-to-1 MUX
Signal types:
Std_logic (single bit), std_logic_vector (buses)
std_logic_vector(7 downto 0) descending range
std_logic_vector(0 to 7) ascending range
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2-to-1 MUX
Single bit assignment:
Y(0) <= 1, use single quotes
Bus assignment:
Y <= 11110000, use double quotes
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Sequential Statement
The process block itself is considered as a single
concurrent statement
Only sequential VHDL statements are allowed within
a process block
Sequential statements:
if else
case
Sensitivity list:
The list of signals after the process block
Any event / change of these signals will cause the process block to be
evaluated
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2-to-1 MUX
Another Architecture Using Process
When using process, common error is forget to
assign a default value to output
If the output is not assigned any value
Synthesizer will assume output must retain current value
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3-to-8-line Decoder
Input:
Binary number D2D1D0
Output:
The output bit corresponds to the input binary number
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3-to-8-line Decoder
Entity:
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3-to-8-line Decoder
Architecture 1
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3-to-8-line Decoder
Architecture 2
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Summary
3 parts of VHDL program:
library, entity, architecture
Concurrent statements
Signal / bus assignment: Z <= A and B;
When else
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Reference
Useful links:
www.gmvhdl.com/VHDL.html
www.vhdl-online.de/tutorial/
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