Instruction Set Architecture

ISA
microprocessors instruction set
set of all assembly language instructions
details of the programmer accessible registers within the
microprocessor.
information necessary to interact with memory
handling interrupts

This Lecture Covers

Different levels of programming languages

Assembly language instructions
Addressing modes
ISA
Factors to be considered in designing the instruction set and
register set
Relatively Simple CPU

Levels of Programming Languages

1. High-level languages
Hides the details of the computer and operating system
Platform independent
C++, Java, Fortran, etc.
2. Assembly languages
Much lower level of abstraction
Instructions can directly manipulate the data stored in a
microprocessors internal components
Not platform-independent
3. Machine languages
Lowest level of programming languages
Platform-specific

Compilation process for high-level programs

High-level language
program (C++, Fortran, etc.

Compiler for Pentium

Windows PC
Other
Pentium
Object files

Pentium
Object code

Compiler for G4
Power Mac Computer
Other
G4
Object files

G4
Object code

Compiler for SPARC

UNIX workstation
Other
SPARC
Object files

SPARC
Object code

Pentium Linker

G4 Linker

SPARC Linker

Pentium
Executable file

G4
Executable file

SPARC
Executable file

Windows
Pentium PC

G4
Pentium PC

SPARC
UNIX workstation

Assembly process for assembly language programs

Assembly language
Program for processor X

Assembler for
Processor X

Processor X
Object code

Other processor X
Object files

Process X
Linker

Processor X
Executable file

Computer with
processor X

Compilation process for Java applets

Java applet
Source code

Java compiler

Byte code

Java VM for
Windows Pentium PC

Java VM for
G4 Power Mac

Java VM for
SPARC UNIX workstation

Windows
Pentium PC

G4
Power Mac

SPARC
UNIX workstation

Assembly Language Instructions

Instruction Types
Data Transfer Instructions
Load data from memory
Store data from the microprocessor into memory
Move data within the microprocessor
Input data to the microprocessor
Output data from the microprocessor
Data Operation Instruction
Arithmetic instructions
Logic instructions

Assembly Language Instructions

Data Types
1. Numeric
Integer
Unsigned (0 to 2n-1)
Signed (-2n-1 to 2n-1 1 inclusive)
Floating point
2. Boolean
3. Character
ASCII
EBCDIC
Unicode

Assembly Language Instructions

Addressing Modes
1. Direct
0: LDAC 5 ;instruction gets data from location 5
. . .
5: 10
;stores value in CPU

2. Indirect
0: LDAC 5 ;instruction gets data from location 5
. . .
5: 10
;then gets data from location 10
. . .
10: 20
;stores value in CPU

3. Register direct
0: LDAC R ;instruction gets address from register R
. . .
R: stores value in CPU

Assembly Language Instructions

Addressing Modes
4. Register indirect
O: LDAC R
. . .
R: 5
. . .
5: 10

;instruction gets address from register R

;then gets data from location 5
;stores value in CPU

5. Immediate
0: LDAC #5 ;stores value from instruction in CPU

6. Implicit
0: LDAC (implicit)
;instruction gets value from stack
. . .
stack -> stores value in CPU

Assembly Language Instructions

Addressing Modes
7. Relative
0:
1:
5:
6:

LDAC $5
instruction adds address of next instruction (1) to
offset (5) to get address (6)
12 -> stores value in CPU

8. Indexed
0: LDAC 5(X)
;instruction gets value from index
register
. . .
X: 10
; then adds contents of X(10) to offset
(5) to get address (15)
. . .
15: 30 -> stores value in CPU

Assembly Language Instructions

Instruction Formats
1. Three-operand
4 bits

2 bits

2 bits

2 bits

opcode

operand
#1

operand
#2

operand
#3

ADD A,B,C (A=B+C)

1010

Assembly Language Instructions

Instruction Formats
2. Two-operand
4 bits

2 bits

2 bits

opcode

operand
#1

operand
#2

MOVE A,B

(A=B)

1010 00 01

ADD

(A=A+C)

1010 00 10

A,C

Assembly Language Instructions

Instruction Formats
3. One-operand
4 bits

2 bits

opcode

operand
#1

LOAD B

(Acc=B)

0000 01

ADD C

(Acc=Acc+C) 1010 10

STORE A

(A=Acc)

0001 00

Assembly Language Instructions

Instruction Formats
3. Zero-operand
4 bits
opcode
PUSH B

(Stack=B)

0101

PUSH C

(Stack=C,B) 0110

ADD

(Stack=B+C) 1010

POP A

(A=Stack)

1100

Instruction Set Architecture Design

A poorly designed ISA, even if it is implemented well, leads to a bad
microprocessor. A well-designed ISA, can result in a powerful
microprocessor that can meet a variety of needs.
ISSUES

What should the instruction set architecture and its

processor be able to do?
Instruction set completeness
General-purpose computing
Special-purpose
Orthogonality
Instructions do not overlap, providing programmers
with the necessary functions in a minimum of
instructions.
Register set

Instruction Set Architecture Design

ISSUES

Does the processor have to be backward compatible with

other microprocessors?
What types and sizes of data will the microprocessor deal
with?
Are interrupts needed?
Are conditional instructions needed?

A Relatively Simple Instruction Set Architecture

1. Memory model
64K x 8 of memory (216 memory locations)
2. I/O
Memory-mapped
3. Registers
Accumulator (AC) register
8-bit register that receives the result of any arithmetic or
logical operation.
Provides one of the operands for 2-operand instruction
Storage for data going to/coming from memory

A Relatively Simple Instruction Set Architecture

continued
3. Registers
R register
8-bit general-purpose register
Supplies the second operand of all 2-operand arithmetic
and logical instructions.
Used to store data that the accumulator will soon need to
access.

A Relatively Simple Instruction Set Architecture

continued
3. Registers
Zero (Z) flag
1-bit status register set whenever an arithmetic or logical
instruction is executed.
Set (1) if result is zero, otherwise it is set to 0.

A Relatively Simple Instruction Set Architecture

4. Instruction set

A Relatively Simple Instruction Set Architecture

Instruction format
3-byte format
Instruction code

Byte 1

Low-order 8 bits of

Byte 2

High-order 8 bits of

Byte 3

1-byte format
Instruction code

Byte 1

A Relatively Simple Instruction Set Architecture

Example:
Calculate
n

i
i 0

or

1 2 ... n

A Relatively Simple Instruction Set Architecture

Solution:
High-level
total = 0;
FOR (int i = 0; i<=n; i++) {
total = total + i;
}

Algorithm
1:
2:
3:
4:

total = 0, i = 0
i = i + 1
total = total + i
IF in THEN GOTO 2

A Relatively Simple Instruction Set Architecture

Solution:
RSISA code
CLAC
STAC
STAC
Loop:
LDAC
INAC
STAC
MVAC
LDAC
ADD
STAC
LDAC
SUB
JPNZ

total
i

total = 0, i = 0

i
i = i + 1
i
total
total = total + i
total
n
IF in THEN GOTO Loop
Loop

A Relatively Simple Instruction Set Architecture