INTEGRATED SOLAR ENERGY

HARVESTING AND STORAGE

BALAJI B.S.
I Semester, M.Tech
SJBIT, Bangalore 60.
b.s.balaji22@gmail.com

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Introduction

ISEHS
PRESENTATION
FLOW
Integrated
Passive Components

Analysis

Different trends in Energy storage

Conclusion
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ISEHS INTRODUCTION

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Integrated solar energy harvesting consists of

array energy scavenging photodiodes along with
storage capacitors fabricated on chip using
0.35m process.
Integrated solar energy harvesting is a power
source for ultra low power devices.
The emerging application of Wireless sensor
networks increases the need for ultra low power
design.

ISEHS BACKGROUND
Wireless sensor application in various fields like :

Medicine

Environmental monitoring networks

Military target tracking, and

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detection of chemical and biological weapons.

In wireless systems, the power source is a bottle

neck that limits system lifetime & performance.
It adds manufacturing cost, and increases system
volume and maintenance expenditures.

ISEHS BACKGROUND

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Delivering the power to wireless sensors network

nodes is a significant system design challenge.
To reduce the system cost and volume it is
necessary to integrate the energy harvesting and
storage with data acquisition, data processing,
and communication circuits.
Solar energy harvesting has been proposed to
extend the lifetime of the system beyond the
limitations imposed by batteries.

ISEHS LOW POWER WIRELESS

SYSTEM
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Fig. 1. Low power wireless system powered from energy scavengers

and a battery. Energy sources include solar (Vsolar), mechanical
vibration (Vvibe)and a battery (Vbat). A mux switches between the
unregulated energy sources.

ISEHS PHOTODIODE OPERATION & IV

CHARACTERISTICS
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Fig. 2. Typical characteristics of a photodiode under illumination

along with a schematic. The optimum configuration for harvesting
energy is found with the load resistance RL that maximizes the
product of the current through the diode Im and the voltage across
the diode Vm .

ISEHS DESIGN OF ENERGY

SCAVENGING PHOTODIODES
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Fig. 3. Top view of photodiodes. (a) D1. (b) D2. (c) D3.
(d) Layer key.

Fig. 4. Side view cutaway of

photodiode D2. Metal connected to
p- & n diffusions correspond to top
and
bottom
capacitor
plates,
respectively

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ISEHS PASSIVE COMPONENTS :

INTEGRATED STORAGE
CAPACITORS

Fig. 5. Side view of the optical path

for photodiode D2, dimensions are
approximate for a 0.35-m CMOS
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process

ISEHS CAPACITANCE

CThe
HARACTERIZATION
total capacitance is given by
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where Ev is the energy stored in the capacitor, Vsolar is the voltage difference between the
capacitor plates, and Ct is the total capacitance, which is made up of the metal capacitance Cm
and the diode capacitance Cd.

The voltage at the input of regulator is given by

where Cr is the input capacitance of the regulator and Ct is the storage capacitance

The pn junction capacitance is given by

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where 0 is the built in potential of the junction, Ai is the area, and Pi is the perimeter of the ith
diode.

ISEHS EFFICIENCY

The Optical Efficiency for a single boundary can be written as

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where R is the percent of reflected energy, is the power absorption coefficient, and d is the
average depth of the pn junction.

The Quantum Efficiency for a photodiode can be written as

where Ip is the generated electrical current, q is the charge of an electron, Popt is the incident
optical power, h is Plancks constant, and v is the frequency of the incident light.

The External Efficiency is the product of OE and QE electrical

power out divided by optical power in.
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ISEHS ANALYSIS USING WHITE LIGHT

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Fig. 6. (a) Output power versus incident light intensity and load
resistance. Active area = 3000 m2 , photodiode D1 output power = 400
nW when RL = 500 k and input intensity = 25 kLUX. (b) Photodiode
D2 output power = 600 nW when RL = 400 k and input intensity = 25
kLUX. (c) Photodiode D3 output power = 800 nW when RL = 230 k and
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input intensity = 25 kLUX.

ISEHS ANALYSIS USING

PROTOTYPE
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Fig. 7. Test setup showing photodiode, current starved ring

oscillator, and level shifting output buffer.

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ISEHS ANALYSIS USING

PROTOTYPE
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Fig. 8. (a) Measured plots of D3 showing VOC and ring

oscillator frequency. (b) Measured plots showing VOC and ring
oscillator frequency for two D3 photodiodes stacked in series.
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ISEHS ANALYSIS IN TERMS OF FOM VS

INPUT LIGHT INTENSITY.
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Fig. 9. Measured FOM plotted versus input light intensity.

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ISEHS ANALYSIS USING GREEN

LASER
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Fig. 11. Generated electrical output power for

photodiode D3 versus green laser input light
intensity ( = 532 nm) and load resistance.
Input optical power is for total chip surface.

Fig. 12. Generated electrical output power

for photodiode D1 versus input light
intensity ( = 532 nm)
and load
resistance.
Dashed
line
represents
linearized transfer function. Input optical16
power is calibrated for the photodiode
area.

ISEHS ITRS TECHNOLOGY TRENDS

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Fig. 13. Technology trends from ITRS roadmap. Minimum

printed gate length, minimum pitch for metal interconnect, and
supply voltage over time.

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ISEHS MAJOR AFFECTS

CAPACITANCE SCALING
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Fig. 14. (a) Ultracapacitor capacitance per unit volume versus total capacitance. Dashed
line represents the linear best fit model. (b) Comparison of capacitance density versus
supply voltage for a 10 F capacitor for ultracapacitor technology, theoretical limit (TL1)
of interconnect capacitance, and vertical parallel plate (VPP) interconnect capacitance.
Supply voltage years correspond to the ITRS roadmap.

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ISEHS ENERGY DENSITY & MEASURED

RESULTS
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ISEHS CONCLUSION

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The design D3 with area 150 m x 150 m can deliver

5 W to power the system. D1 needs 184 m x 184 m
and D2 needs 164 m x 164 m to deliver 5 W.
ISEHS may be a viable solution for low energy storage
requirements or cost constraints which limit systemin-package integration.
The combination of integrated solar energy
scavenging and storage can enable a new generation
of low cost, long lifetime, small volume systems for
future wireless sensor networks or RFID applications.

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