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Design
Niraj K. Jha
Dept. of Electrical Engineering
Princeton University
Joint work with: Anish Muttreja and
Prateek Mishra
Talk Outline
Background
Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdds
(TCMS)
Extension of TCMS to Logic Circuits
Conclusions
DG-FETs
Gap
10 nm
Non-Si nano devices
A FinFET is like a FET, but the channel has been turned on its edge
and made to stand up
Si Fin
Independent-gate FinFETs
Oxide insulation
Back Gate
FinFET structure
Ananthan, ISQED05
Talk Outline
Background
Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdds
(TCMS)
Extension of TCMS to Logic Circuits
Conclusions
11
Talk Outline
Background
Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdds
(TCMS)
Extension of TCMS to Logic Circuits
Conclusions
12
SG-mode NAND
pull up bias
voltage
LP-mode NAND
pull down
bias voltage
IG-mode NAND
IG-mode
pull up
IG/LP-mode NAND
LP-mode
pull down
14
Advantages
Disadvantages
SG
LP
IG
IG/LP
FinFET Characteristics
16
B. Swahn and S. Hassoun, ``Gate sizing:FinFETs vs 32nm bulk MOSFETs, in Proc. DAC, 2006
18
Our Approach
32
nm PTM
32nm
PTM
inFET models
FinFET
models
FinFET
models
Logic
Logicgate
gate
designs
designs
Delay/power
characterization in
SPICE
IG
SG
Synopsys libraries
IG/LP
Benchmark
Minimum-delay
synthesis in
Design Compiler
SG-mode
netlist
Power-optimized
mixed-mode netlists
LP
Construct FinFET-based
Synopsys technology libraries
Extend linear programming
based cell selection for FinFETs
Use optimized netlists to
compare logic styles at a range
of delay constraints
Linear programming
based cell selection
SG+
IG/LP
SG+LP
SG+IG
19
Available modes
21
+18.0%
22
Talk Outline
Background
Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdds
(TCMS)
Extension of TCMS to Logic Circuits
Conclusions
23
24
Gate Coupling
Reverse bias
Vgs=+0.08V
Our proposal:
overdriven gates
Overdriven FinFET gates
leak a lot less!
Higher Vth
1.08V
1V
Leakage
current
Vin
Overdriven
inverter
26
TCMS
Using only two Vdds saves leakage only in
P-type FinFETs, but not in N-type FinFETs
Solution
dd
1.08V
VddL
1.0V
VssH
-0.08V
VssL
0.0V
Symmetric
threshold control
for P and N
VssH
VssL
TCMS buffer
28
29
Link Design
SPICE simulation to minimize power consumption in
TCMS link while remaining within 1% of the delay of
the single Vdd link
Parameter
Link
length(lopt)
Inverter
widths
(s1, s2)
Delay (ps)
Single
TCMS
Vdd
0.199m
0.199mm
m
Change
0
42, 84
30, 50
-36.5%
12.19
12.27
0.65%
30
Interconnect Synthesis
Problem: Insert buffers on a given wiring tree to
meet a given delay bound while minimizing total
power consumption
Two types of buffers considered
TCMS buffers
Dual-Vdd buffering scheme
Power Savings
Power
component
Dynamic
power
Leakage
power
Total power
Savings
-29.8%
57.9%
50.4%
http://dropzone.tamu.edu/~zhouli/GSRC/fast_buffer_insertion.html
32
Fin-count Savings
Talk Outline
Background
Motivation: Power Consumption
FinFETs for Low Power Design
Vth Control through Multiple Vdds
(TCMS)
Extension of TCMS to Logic Circuits
Conclusions
34
35
TCMS Extension
H
V
dd =1.08V
H
Vdd
VLdd
V1
H
Vss
H
Vdd
V2
V1'
V2'
VddL=1.0V
VssL
=Gnd
L
Vss
H
Vss
H
V
ss = -0.08V
I D (VGS Vt )
I L exp(VGS Vt )
36
H
Vdd
b
L
Vss
VHss
L
Vdd
b
L
Vss
VHss
38
L
Vdd
b
L
Vss
VHss
39
b
L
Vss
40
Optimization Flow
Combinational gate
level Verilog netlist
Shorted-gate
library
TCMS
library
no
yes
P
no
Optimized netlist
41
Experimental Setup
Switching activity at primary inputs set to 0.1
Temperature: 75oC
Technology node: 32nm
Nominal-Vdd: (1.0V,0V), High-Vdd: (1.08V,-0.08V)
Nominal-Vth: (0.29V,-0.25V),
High-Vth: (0.45V,-0.40V)
Cell libraries characterized using HSPICE based
on PTM1 in Synopsys-compatible format
Interconnect delay and load modeled
5 sizes for logic gates: X1, X2, X4, X8 and X16
42
1
http://www.eas.asu.edu/~ptm/
X2
X8
X1
inv101
X2
nor11011
X1
b
X1
nor10011
X2
X8
X1
nor01100
X2
inv101
X16
inv101
X8
X8
X4
X16
X4
a
X8
X16
Level:
X2
d
X16
nand01001
inv101
X2
inv101
X8
X1
nor00111
X4
nor01100
nor10011
nand00110
X2
X1
X2
X8
2
inv101
4
Level :
Delay-minimized netlist
Power : 283.6uW (leakage power:
10.3uW, dynamic power: 273.3uW)
Area: 538 fins
Power-optimized netlist
Power : 149.9uW (leakage power: 2.0uW,
dynamic power: 147.9uW)
43
Area: 216 fins
44
45
46
Conclusions
FinFETs are a necessary step in the evolution of
semiconductors because bulk CMOS has difficulties in
scaling beyond 32 nm
Use of the back gate leads to very interesting design
opportunities
Rich diversity of design styles, made possible by
independent control of FinFET gates, can be used
effectively to reduce total active power consumption
IG/LP mode circuits provide an encouraging tradeoff
between power and area
TCMS able to reduce both delay and subthreshold
leakage current in a logic circuit simultaneously
47