Overview: Testability Evaluation: Outline

Overview: Testability Evaluation
Outline
Quality Policy of Electronic Design
Tradeoffs of Design for Testability
Testability measures
Heuristic measures
Probabilistic measures
Calculation of testability
Parker - Mc Cluskey method
Cutting method
Conditional probabilities based method
Technical University Tallinn, ESTONIA
Raimund Ubar
Quality Policy
Chips from
manufactory
Yield
For example 60%, other chips are faulty

Testimine
Defect level
How many chips from
hundred escape?
2
Introduction: The Problem is Money?

Cost
Cost of
testing
Cost of
the fault
How to succeed?
Try too hard!
How to fail?
Try too hard!
(From American Wisdom)
Test
coverage
function
Fault Coverage
Cost of quality
Time
Time
Conclusion:
Quality
0%
Optimum
test / quality
100%
The problem of testing

can only be contained
not solved
T.Williams
Design for Testability

The problem is - QUALITY:
Yield (Y)
P,n
Quality policy
Design for testability

Testing
Y (1 P )
Defect level (DL)

Pa
P - probability of a defect
n - number of defects
Pa - probability of accepting
a bad product
- probability of producing a good product

The problem is - QUALITY:
Yield (Y)
P,n
Defect level (DL)
Quality policy
Pa
Pa
nm
DL
(
1
P
)
1 Y
n
(1 P ) Pa
nm
n
n - number of defects
Pa
m - number of faults tested
P - probability of a defect
Pa - probability of accepting a bad product
T - test coverage
1 Y
(1
m
)
n
1 Y (1T )
(1 P ) (1 P )
m
Y (1 P ) n

The problem is - Money:
DL 1 Y
DL
Y
Y(%)
T(%)
0
Goal:
(1T )
100
90
50
45
25
10
81
45
DL T Testability
Paradox: Testability
10
50
90
DL (Y )
T(%)

Tradeoffs:
Goal: DL T Testability
Paradox: Testability DL (Y )
DFT: Resynthesis or
adding extra hardware
Performance
Economic tradeoff:
C (Design + Test) < C (Design) + C (Test)
Logic complexity
Area
Number of I/O
Power consumption
Yield

Economic tradeoff:
C (Design + Test) < C (Design) + C (Test)
C (DFT) + C (Test) < C (Design) + C (Test)
C (Test) = CTGEN + (CAPLIC + (1 - Y) CTS) Q
Test generation
Testing
Troubleshooting
Volume
Design
Product
C (DFT) = (CD + CD) + Q(CP + CP)

Testability Criteria
Qualitative criteria for Design for testability:
Testing cost:
Test generation time

Test application time
Fault coverage
Test storage cost (test length)
Availability of Automatic Test Equipment
Redesign for testability cost:

Performance degradation
Area overhead
I/O pin demand
Testability of Design Types

General important relationships:
T (Sequential logic) < T (Combinational logic)
Solutions: Scan-Path design strategy
T (Control logic) < T (Data path)

Solutions: Data-Flow design, Scan-Path design strategies
T (Random logic) < T (Structured logic)

Solutions: Bus-oriented design, Core-oriented design
T (Asynchronous design) < T (Synchronous design)

T (Sequential logic) < T (Combinational logic
IN
OUT
Combinationa
l circuit
Solution: Scan-Path design strategy

q
IN
OUT
Combination
al circuit
Scan-IN
Scan-OUT

T (Control logic) < T (Data path)
Control Part
y1
R1
y3
M1
M2
M3
y4
IN
y2
Solutions:
Scan-Path design strategie
Data-Flow design
e
R2
Data Part
Raimund Ubar
Scan-Path Based Testing

How to test million transistors?
Multi Site Test
All memory components are made

transparent via shift registers
System
ATE
Response
H.-J.Wunderlich, U Stuttgart
Fault
Test
patterns
Test

T (Random logic) < T (Structured logic)
Solutions: Bus-oriented design, Core-oriented design
Sea of gates
Sequence of
216 bits
&
16 bit
counter
1
System
Testability Estimation Rules of Thumb

Circuits less controllable
Circuits less observable
Decoders
Circuits with feedback
Counters
Clock generators
Oscillators
Self-timing circuits
Self-resetting circuits
Circuits with feedback

Embedded
RAMs
ROMs
PLAs
Error-checking circuits
Circuits with redundant
nodes
Bad Testability: Fault Redundancy

Redundant gates (bad design):
x1
Internal signal dependencies:
&
x2
x4
&
1
&
x3
&
&
Faults at
x2 is not testable
Optimized function:
y x1 ( x1 x2 ) x4 x3 x4
y
0
x2
&
1
&
Impossible pattern,
OR XOR is not testable
y x1 x4 x3
Raimund Ubar
CREDES Summer School
Fault Redundancy
Hazard control circuit:
1
&
01
&
&
0
Error control circuitry:
01
10
Decoder
1
101
Hazard
Redundant AND-gate
Fault 0 is not testable
1
E=1
E = 1 if decoder is fault-free
Fault 1 is not testable
17
Raimund Ubar
Fault Redundancy
Redundant gates
(bad design):
x1
x2
&
1
&
&
x41
&
Faults at x2 are
not testable, the
node is redundant
&
x3
x4
y x1 ( x1 x2 ) x4 x3 x4
y
0
x2
&
x12
&
x3
x4
x11
x1
x42
&
&
y x11 x12 x41 x3 x42

y
1
x42
Fault
if
x4 0
x42 0 is not testable
18
Raimund Ubar
Fault Redundancy
Redundant gates
(bad design):
x11
x1
x11
x1
&
x12
x41
x12
1
&
x3
x4
x42
&
&
y
1
x42
x4
&
x3
y x11 x12 x41 x3
y x11 x12 x41 x3 x42
Fault
&
if
x4 0
y
1
x12
Fault
if
x1 1
Final result of optimization:
y x1 x4 x3
x1
x4
x3
y
19
Testability Measures
Evaluation of testability:
Controllability for 1 needed
Controllability
C0 (i)
C1 (j)
Observability
OY (k)
OZ (k)
Testability
1
2
20
1
2
20
&
1
i
j
x
1
2
k 20
&
1
2
20
&
Defect
Probability of detecting 1/260
Heuristic Testability Measures

Controllability calculation: AND gate
Measure: minimum number of nodes that must be set to produce 0
For inputs: C0(x) = C1(x) = 1
For other signals: recursive calculation starting from inputs
C0(x1) = 1
C0(x2) = 1
C0(xi) = 23
C0(xk) = min [C0(xi), C0(xj) ] + 1 =

= min (23,11) + 1 = 12
C0(xj) = 11

Controllability calculation: OR gate
C0(x1) = 1
C0(x2) = 1
C0(xi) = 23
1
C0(xj) = 11
C0(xk) = C0(xi) + C0(xj) + 1 =

= 23 + 11 + 1 =
35

Controllability calculation:
C1(x1) = 1
C1(x2) = 1
C1(xi) = 23
&
C1(xk) = C1(xi) + C1(xj) + 1 =

= 23 + 11 + 1 = 35
C1(xj) = 11

Controllability calculation: EXOR gate
Measure: minimum number of nodes that must be set in order to produce 0
C0(xi) = 23
C0(x1) = 1
C0(x2) = 1
C1(xi) = 18
C0(xj) = 12
C0(xk) = min { [ C0(xi) + C0(xj) ], [C1(xi)

+ C1(xj) ] } + 1 =
+12), (18 + 20) } + 1 =
+ 1 = 36
min{ (23
min (35,38)
C1(xj) = 20

Measure: minimum number of nodes that must be set in order to produce 0 or 1
For other signals: recursive calculation rules:
&
C0(y) = C1(x) + 1
C1(y) = C0(x) + 1
x1
x2
x1
x2
&
C0(y) = minC0(x1), C0(x2) + 1

C1(y) = C1(x1) + C1(x2) + 1
x1
x2
C1(y) = minC1(x1), C1(x2) + 1

C0(y) = C0(x1) + C0(x2) + 1
C0(y) = min(C0(x1) + C0(x2)), (C1(x1) + C1(x2)) + 1

C1(y) = min(C0(x1) + C1(x2)), (C1(x1) + C0(x2)) + 1

Observability calculation:
Measure: minimum number of nodes which must be set for fault propagating
For outputs: O(y) = 1
O(xi) = O(xk) + C1(xj) =

= 23 + 11 + 1 = 35
O(xk) = 23
O(y) = 1
C1(xj) = 11

Observability calculation:
Measure: minimum number of nodes which must be set for fault propagating
For outputs: O(y) = 1
&
O(x) = O(y) + 1
x1
x2
&
O(x1) = O(y) + C1(x2) + 1
x1
x2
O(x1) = O(y) + C0(x2) + 1
x1
x2
O(x1) = O(y) + 1

Testability calculation:
Measure: sum of controllability and observability
T(x 0) = C1(x) + O(x)

T(x 1) = C0(x) + O(x)
T(xi = 0) = O(xi) + C1(xj) = 35 + 16 = 51

O(xi) = 35
C1(xi) = 16
O(xk) = 23
O(y) = 1
C1(xj) = 11

Controllability and observability:
Macro
1
2
3
4
5
71
&
&
a
&
72
&
b
&
73
&
&
x
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Controllabilies
C0(x)
C1(x)
1
1
1
1
1
1
1
1
1
1
1
1
3
2
3
2
3
2
3
2
4
2
4
2
4
2
4
2
5
5
8
5
Obs.
O(x)
10
12
11
11
10
10
9
11
9
9
9
7
7
7
4
1

Testability calculation:
T(x 0) = C1(x) + O(x)
T(x 1) = C0(x) + O(x)
Macro
1
2
3
4
5
71
&
&
a
&
72
&
b
&
73
&
&
x
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Controllabilies
C0(x)
C1(x)
1
1
1
1
1
1
1
1
1
1
1
1
3
2
3
2
3
2
3
2
4
2
4
2
4
2
4
2
5
5
8
5
Obs.
O(x)
10
12
11
11
10
10
9
11
9
9
9
7
7
7
4
1
Testab.
T(x0)
11
13
12
12
11
11
11
13
11
11
11
9
9
9
9
6
Probabilistic Testability Measures

Measure: probability to produce 0 or 1 at the given nodes
For inputs: C0(i) = p(xi=0) = 1 - pxi
C1(i) = p(xi=1) = 1 - p(xi=0) = pxi
&
py = 1 - p x
p y p xi
i 1
&
py= px1 px2
x1
x2
py= 1 - (1 - px1)(1 - px2)
x1
xn
..
.
&
..
.
x1
xn
x1
x2
p y 1 (1 p xi )
i 1

Probabilities of reconverging fanouts:
x1
x2
x1
x2
py = (1 px1 ) px2 + (1 px2) px1
= 0,25 + 0,25 = 0,5

&
py = 1 - (1 - pa ) (1 - pb)
y
1
&
= 1 - 0,75*0,75 = 0,44
b
Signal correlations:
x
&
py= px px = px2
Calculation of Signal Probabilities

Parker - McCluskey
algorithm:
py = 1 - (1 - pa ) (1 - pb) =
= 1 - (1 - px1(1 - px2))(1 - px2(1 - px1)) =
= 1 - (1 - px1+ px1px2) (1 - px2+ px1px2) =
= 1 (1 - px2+ px1px2 - px1 + px1 px2 - p2x1 px2 +
x1
x2
&
+ px1px2 - px1 p2x2 + p2x1 p2x2) =

1
&
= 1 (1 - px2+ px1px2 - px1 + px1 px2 - px1 px2 +

+ px1px2 - px1 px2 + px1 px2) =
= px2- px1px2 + px1 - px1 px2 + px1px2 - px1px2 + px1 px2 - px1 px2 ) =
= px1 + px2 - 2px1px2 = 0,5

Straightforward methods:
Calculation gate by gate:
21 &
pa = 1 p1p2 = 0,75,
&
22
&
pb = 0,75, pc = 0,4375, py = 0,22
&
23
Parker - McCluskey algorithm:

py = pcp2 = (1- papb) p2 =
= (1 (1- p1p2) (1- p2p3)) p2 =
For all inputs: pk = 1/2
= p1p2 2 + p22p3 - p1p23p3 =

= p1p2 + p2 p3 - p1p2p3 = 0,38

Parker-McCluskey:
Observability:
p(y/a = 1) = pb p2 =
21 &
= (1 - p2p3) p2 = p2 - p22p3
x
&
22
&
= p2 - p2p3 = 0,25
Testability:
&
23
p(a 1) = p(y/a = 1) (1 - pa) =

= (p2 - p2p3)(p1p2) =
= p1p22 - p1p22p3 =
= p1p2 - p1p2p3 = 0,125

Cutting method
Idea:
Complexity of exact
calculation is reduced by
using lower and higher
bounds of probabilities
Technique:
Reconvergent fan-outs are
cut except of one
Probability range of [0,1] is
assigned to all the cut lines
The bounds are propagated
by straightforward
calculation
1
2
3
4
5
71
&
&
&
a
&
72
&
b
&
73
&
Lower and higher bounds for the

probabilities of the cut lines:
p71 := (0;1), p72 := (0;1), p73 := 0,75
For all inputs: pk =

0,5
Reconvergent fanouts are cut except
of one 71 and 72
Probability range of
[0,1] is assigned to
all the cut lines - 71
and 72
The bounds are
propagated by
straightforward
calculation
1
2
3
4
5
6
1/2
[0,1] 71
&
&
72
&
3/4
73
3/4 &
1/2 &
a
[1/2,1]
&
[1/2,1]
c
Calculation steps:
pk [pLB , pHB) Exact pk
p7
3/4
3/4
p71
[0, 1]
3/4
p72
[0, 1]
3/4
p73
3/4
3/4
pa
[1/2, 1]
5/8
[1/4,3/4]
1/2
Cutting method
d
[1/2,3/4]
5/8
pk
pb
pc
pd
pe
py
&
y [34/64,54/64]
Exact value:
41/64
[pLB , pHB)
[1/2, 1]
5/8
[1/2, 3/4]
[1/4, 3/4]
[34/64, 54/64 ]
Exact pk
5/8
5/8
11/16
19/32
41/64

Method of conditional
probabilities
Probabilitiy for y
Conditions x set of conditions
p( y)
p( y /( x i) p( x i)
i( 0 ,1)
P(y) = p(y/x=0) p(x=0) + p(y/x=1) p(x=1)
Conditional probabilitiy
Idea of the method:

Two conditional probabilities are calculated along the paths (NB! not bounds as in
the case of the cutting method)
Since no reconvergent fanouts are on the paths, no danger for signal correlations

Method of conditional
probabilities
p( y )
p( y /( x i) p( x i)
i( 0 ,1)
1
2
3
4
5
71
7 72
&
3/4
&
&
73
&
x
NB! Probabilities
Pk = [Pk* = p(xk/x7=0), Pk ** = p(xk/x7=1)]

are propagated, not bounds
as in the cutting method.
&
a
[1,1/2]
[Pk* , Pk**]
[1, 1/2]
&
e
[1/2,5/8]
[1,1/2]
&
Pk
Pb
Pc
Pd
Pe
Py
[1/2,11/16]
[1,1/2]
Pk
P7
P71
P72
P73
Pa
d
[1/2,3/4]
[Pk* , Pk**]
[1, 1/2]
[1, 1/2]
[1/2, 3/4]
[1/2, 5/8]
[1/2, 11/16 ]
py = p(y/x7=0)(1 - p7) + p(y/x7=1)p7 = (1/2 x 1/4) + (11/16 x 3/4) = 41/64


Using BDDs:
21 &
py = p(L1) + p(L2) =
&
= p1 p21 p23 + (1 - p1) p22 p3 p23 =

= p1 p2 + p2 p3 - p1p2 p3 = 0,38
21
&
&
L1
23
p2 p1
y
L2
22
22
23
p1 p21 p23
3
3
(1-p1)p22p3p23
p2(1-p1)p3
Calculating Probabilities on BDDs
py =
1
2
px
21
&
&
22
LkL(1)
xXk
&
&
23
Example:
21
23
L1 = (1,21,23)
L2 = (1,22,3,23)
L1
L2
22
py = p1p2 + p1p2p3 = 0,375

Heuristic and Probabilistic Measures

Heuristic controllability measure:
CC1[y] =
min
CC1 (x(m) } + const.
k: lkL(1) mMk
Probabilistic measure:
py =
k: LkL(1)
xXk
21
px
23
L1
L2
22
Heuristic Controllabilities
Using BDDs for controllability
calculation:
BDD-based algorithm
for the heuristic
measure is the same
as for the probabilistic
measure
21 &
Gate level calculation

x
C0(x) C1(x)
a
3
2
b
3
2
c
5
4
y
2
6
a
&
22
&
c
y
&
23
C1(y) = min [(C1(L1), C1(L2)] + 1 =

= min [C1(x1) + C1(x2),
y
1
21
23
L1
L2
C0(x1) + C1(x2) + C1(x3)] + 1 =

= min [2, 3] + 1 = 3
22

Using BDDs:
21 &
Observability:
&
p(y/x21 = 1) = p(L1) p(L2) p(L3) =

= p1 p23 (1 - p3) = 0,125
22
= p21 p(L1) p(L2) p(L3) =

= p2p1 (1 - p3) = 0,125
Why: p(y/x21 = 1) = p21 p(y/x21 = 1)?
&
&
23
Testability:
p(x21 0) = p21 p(y/x21 = 1) =
L1
L2
21
22
23
L3
Calculating Observabilities on BDDs

Macro
1
2
3
4
5
6
71 &
&
&
a
&
7 72
&
&
b
c
73
&
73
1
2
71
72
y/x(m) = L(m0,m) L(m1, mT,1) L(m0, mT,0)

p(y/x(m)=1)=p(m0,m) p(m1,mT,1) p(m0,mT,0)
Calculating Observabilities on BDDs

Macro
1
2
71
3
4
5
&
&
&
&
73
73
71
72
2
2 7
1
5
5
1/64
1/64
2
1
2
2
2
5
6
&
73
Calculation procedure:
&
7 72
&
72
2
2
1/64
1/64
4/64
1/64
1/64
1/64
p(y/x1= 1) = 11/64

Combining BDDs and conditional probabilities
w
y
z
Using BDDs gives correct results only inside the blocks,
not for the whole system
New method:
Block level: use BDDs and straightforward calculation
System level: use conditional probabilities
Register Transfer Level and DDs

Superposition of word-level DDs:
R2
y1
y3
R1
M1
M2
y4
R2
c
M3
IN
y2
y4
y3
R2
1
2
y1
R1 + R 2
IN + R 2
IN
R1
y2
0
1
R1 * R 2
IN* R2
Calculating RT-Level Observabilities

Terminal nodes
data-path):
Gate-level calculation:
py =
LkL(1)
px
R2
y4
0
1
xXk
RT-level calculation:
P(y=z(m )) =
P(x=e)
LiL(m0,m ) xXi
0
R2
0
y3
P(R2= R1 R2) = P(y4=2) P(y3=3) P(y2=0)
R1 + R2
1
1
2
Example:
y1
IN + R 2
IN
R1
y2
0
1
R 1* R 2
IN* R 2
Calculating RT-level Probabilities

Gate-level calculation:
LkL(1)
xXk
py = p(y=1) =
Nonterminal nodes
(control-path):
px
RT-level calculation:
1
xA
0
1
P(y=k) =
LiL(k)
Example:
P(x=e)
xXi
3,4
xB
1
4
2
5
3
P(q=5) = P(q=2)P(xB=0) + P(q=3) + P(q=4)


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Overview: Testability Evaluation

Technical University Tallinn, ESTONIA

For example 60%, other chips are faulty

Introduction: The Problem is Money?

The problem of testing

Design for Testability

Design for testability

Defect level (DL)

- probability of producing a good product

Technical University Tallinn, ESTONIA

Design for Testability

Defect level (DL)

Technical University Tallinn, ESTONIA

Design for Testability

Design for Testability

Technical University Tallinn, ESTONIA

Design for Testability

C (DFT) = (CD + CD) + Q(CP + CP)

Test generation time

Redesign for testability cost:

Technical University Tallinn, ESTONIA

Testability of Design Types

T (Control logic) < T (Data path)

T (Random logic) < T (Structured logic)

T (Asynchronous design) < T (Synchronous design)

Technical University Tallinn, ESTONIA

Testability of Design Types

Solution: Scan-Path design strategy

Technical University Tallinn, ESTONIA

Testability of Design Types

Technical University Tallinn, ESTONIA

Scan-Path Based Testing

All memory components are made

Testability of Design Types

Technical University Tallinn, ESTONIA

Testability Estimation Rules of Thumb

Circuits less observable

Circuits with feedback

Technical University Tallinn, ESTONIA

Bad Testability: Fault Redundancy

CREDES Summer School

Error control circuitry:

CREDES Summer School

y x11 x12 x41 x3 x42

x42 0 is not testable

CREDES Summer School

y x11 x12 x41 x3

y x11 x12 x41 x3 x42

x42 0 is not testable

x12 1 is not testable

Final result of optimization:

Technical University Tallinn, ESTONIA

Heuristic Testability Measures

C0(xk) = min [C0(xi), C0(xj) ] + 1 =

Technical University Tallinn, ESTONIA

Heuristic Testability Measures

C0(xk) = C0(xi) + C0(xj) + 1 =

Technical University Tallinn, ESTONIA

Heuristic Testability Measures

C1(xk) = C1(xi) + C1(xj) + 1 =

Technical University Tallinn, ESTONIA

Heuristic Testability Measures

C0(xk) = min { [ C0(xi) + C0(xj) ], [C1(xi)