CS2100 Computer Organisation

Basic Datapath

REVIEW: EDGE-TRIGGERED D FLIP-FLOP

Value of D is sampled on negative clock edge.

Q outputs sampled value for the rest of cycle.

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Basic Datapath

REVIEW: D LATCH VS D FLIP FLOP

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Basic Datapath

SINGLE CYCLE DATAPATH

T
clk

All instructions
execute in a single
cycle of the clock
(negative edge to
negative edge)
Not used in reality! Only for teaching purposes.
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Basic Datapath

THE INSTRUCTION PROCESSING CYCLE

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Basic Datapath

INSTRUCTION FETCH
Obtain

the instruction to be executed

From where?
Ans: where PC is pointing to!
Need to read from instruction memory (main memory)

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Basic Datapath

INSTRUCTION DECODE
Decode instruction to find out what to do
Input: the instruction to be executed
Output: the control signals to the other parts of
the processor telling various units what to do so
that together they execute this instruction

Examples: what register(s) to read, what ALU

operation to perform

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Basic Datapath

OPERAND FETCH
Get the operands needed by the instruction to
compute on
Read from the registers

Registers are kept together in the register file (RISC

architecture)

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Basic Datapath

EXECUTE

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Do it!

Basic Datapath

RESULT STORE
Write

result of computation back to the

register file

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THE INSTRUCTION PROCESSING CYCLE

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THE PROCESSOR: DATAPATH &

CONTROL

Our implementation of the MIPS is simplified

memory-reference instructions: lw, sw
arithmetic-logical instructions: add, sub, and, or, slt
control flow instructions: beq, j

Generic implementation
use the program counter (PC) to supply the
instruction address and fetch the instruction
from memory (and update the PC)
decode the instruction (and read registers)
execute the instruction

Fetch
PC = PC+4

Exec

Decode

All instructions (except j) use the ALU after reading the

registers
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CLOCKING METHODOLOGIES

The clocking methodology defines when signals can be

read and when they are written
An edge-triggered methodology

Typical execution
read contents of state elements
send values through combinational logic
write results to one or more state elements

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CLOCKING METHODOLOGIES
State
element
1

Combinational
logic

State
element
2

clock

one clock cycle

Assumes state elements are written on every clock

cycle; if not, need explicit write control signal
write occurs only when both the write control is asserted and the
clock edge occurs

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FETCHING INSTRUCTIONS

Fetching instructions involves

reading the instruction from the Instruction Memory
updating the PC to hold the address of the next
instruction

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FETCHING INSTRUCTIONS

Add
4
Instruction
Memory
PC

Read
Address

Instruction

PC is updated every cycle, so it does not need an explicit

write control signal
Instruction Memory is read every cycle, so it doesnt need an
explicit read control signal
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SEQUENTIAL LOGIC

Add
4
Instruction
Memory
PC

Read
Instruction
Address

CLK

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SEQUENTIAL LOGIC

Add
4
Instruction
Memory
PC

Read
Instruction
Address

CLK

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SEQUENTIAL LOGIC
Add
4
Instruction
Memory
PC

Read
Instruction
Address

CLK

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FETCHING STRAIGHT LINE CODE

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THE FIRST REGISTER - PC

Build from an array of D-flip-flops

CLK
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DECODING INSTRUCTIONS

Decoding instructions involves

sending the fetched instructions opcode and function field
bits to the control unit

Control
Unit

Instruction

Read Addr 1
Read
Register
Read Addr 2 Data 1
File
Write Addr
Read
Write Data

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Data 2

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DECODING INSTRUCTIONS

reading two values from the Register File

Register File addresses are contained in the instruction

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DEMAND ON THE REGISTER FILE

Must be able to:

Read two registers
Write one register

at the same time!

Technically, we need two read ports and one write port
Each port includes
Register number to be read from/written to
Control signals

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REGISTER FILE
sel(rs1)

CLK

R0 the constant 0

sel(ws)

EN

R1

.
.
.
32

WE

D
E
M
U
X

EN

R2

D
32

wd

M
U
X

32

rd1

.
.
.
EN

32

sel(rs2)
5

32

R31

.
.
.
32

M
U
X

32

One write port

Two read ports

rd2

EXECUTING R FORMAT OPERATIONS

R format operations (add, sub, slt, and, or)

31
R-type: op

25
rs

20

15

rt

rd

10

shamt funct

perform the (op and funct) operation on values in rs and rt

store the result back into the Register File (into location rd)

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EXECUTING R FORMAT OPERATIONS

RegWrite

Instruction

ALU control

Read Addr 1
Read
Register
Read Addr 2 Data 1
File
Write Addr
Read
Write Data

ALU

overflow
zero

Data 2

The Register File is not written every cycle (e.g. sw), so we need
an explicit write control signal for the Register File

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THE ALU

A combination of adder, multiplier, shifter, logical

operations etc.
Operations to be done selected by control signals
Control signals generated during decode time

Additional outputs
Is it zero?
Did an overflow occur?
Typically the flags:

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Zero
Carry
Overflow
Negative
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DEALING WITH IMMEDIATES

Some MIPS instructions require zero-extension, some require sign extension

- control signals have to be generated during decode
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EXECUTING LOAD AND STORE

OPERATIONS

Load and store operations involves

compute memory address by adding the base register (read from
the Register File during decode) to the 16-bit signed-extended
offset field in the instruction
store value (read from the Register File during decode) written to
the Data Memory
load value, read from the Data Memory, written to the Register File

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EXECUTING LOAD AND STORE

OPERATIONS
RegWrite

Instruction

16

Address
ALU

Data
Memory Read Data
Write Data

Data 2

Sign
Extend

MemWrite

overflow
zero

Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data

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ALU control

MemRead
32

Basic Datapath

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ADDING MEMORY OPERATIONS

Instruction
Fetch

Instruction
Fetch

Instruction
Decode

Instruction
Decode

Operand
Fetch

Operand
Fetch

Execute
Execute
Memory
Read/Write

Result
Store

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Result
Store
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EXECUTING BRANCH OPERATIONS

Branch operations involves

compare the operands read from the Register File during decode for
equality (zero ALU output)
compute the branch target address by adding the updated PC to the
16-bit signed-extended offset field in the instr

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EXECUTING BRANCH OPERATIONS

Add
4

Add

Shift
left 2

Branch
target
address

ALU control
PC

Instruction

Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data

16

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ALU

Data 2

Sign
Extend

Basic Datapath

zero (to branch

control logic)

32

34

EXECUTING JUMP OPERATIONS

Jump operation involves

replace the lower 28 bits of the PC with the lower 26 bits of the
fetched instruction shifted left by 2 bits

Add
4

4
Instruction
Memory

PC

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Read
Address

Instruction

Basic Datapath

Shift
left 2

Jump
address
28

26

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CREATING A SINGLE DATAPATH

FROM THE PARTS

Assemble the datapath segments and add control

lines and multiplexors as needed

Single cycle design fetch, decode and execute each

instructions in one clock cycle
no datapath resource can be used more than once per
instruction, so some must be duplicated (e.g., separate
Instruction Memory and Data Memory, several adders)
multiplexors needed at the input of shared elements with
control lines to do the selection
write signals to control writing to the Register File and Data
Memory

Cycle time is determined by length of the longest path

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FETCH, R, AND MEMORY ACCESS

PORTIONS
Add

RegWrite

ALUSrc ALU control

4
Instruction
Memory
PC

Read
Address

Instruction

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Address
ALU

Data
Memory Read Data
Write Data

Data 2

Sign
Extend
16

MemtoReg

ovf
zero

Read Addr 1
Register Read
Read Addr 2 Data 1
File
Write Addr
Read
Write Data

MemWrite

MemRead
32

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ADDING THE CONTROL

Selecting the operations to perform (ALU, Register

File and Memory read/write)

Controlling the flow of data (multiplexor inputs)

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ADDING THE CONTROL

31

Observations

R-type: op
31

25
rs
25

20

15

rt

rd

20

10

shamt funct

15

op field always I-Type: op

address offset
rs
rt
in bits 31-26
31
25
addr of registers J-type:
op
target address
to be read are
always specified by the
rs field (bits 25-21) and rt field (bits
20-16); for lw and sw rs is the base register
addr. of register to be written is in one of two places in rt (bits
20-16) for lw; in rd (bits 15-11) for R-type instructions
offset for beq, lw, and sw always in bits 15-0
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SINGLE CYCLE DATAPATH WITH CONTROL UNIT

0
Add
Add
4

Shift

PCSrc

left 2

ALUOp

Branch

MemRead

Control
Unit

Instr[31-26]

MemtoReg
MemWrite
ALUSrc
RegWrite

RegDst

ovf
Instruction
Memory
PC

Read
Address

Instr[31-0]

Instr[25-21]

Read Addr 1

Instr[20-16]

Register
Read Addr 2
File

0
1
Instr[15
-11]

Write Addr

Read
Data 1

Address

zero
0

Read
Data 2

Write Data

Write Data

Sign
Extend

Instr[15-0]
16

ALU

Data
Memory

32
Instr[5-0]

ALU
control

Read Data

1
0

R-TYPE INSTRUCTION
DATA/CONTROL FLOW

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LOAD WORD INSTRUCTION

DATA/CONTROL FLOW

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BRANCH INSTRUCTION
DATA/CONTROL FLOW

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ADDING THE JUMP OPERATION

Controls
RegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOp2

Jump

R-type
000000

lw
100011

sw
101011

beq
000100

j
000010

Instruction [31-26]

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ALU operations
Assume

4 bit ALU control lines

0000 AND
0001 OR
0010 add
0110 subtract
0111 set less than
1100 NOR

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How ALU depends on ALUop

OPcode

ALUop

Operation

Funct field

Desired op

ALU control

lw

00

load word

XXXXXX

add

0010

sw

00

store word

XXXXXX

add

0010

beq

01

branch eq

XXXXXX

subtract

0110

R-type

10

add

100000

add

0010

R-type

10

subtract

100010

subtract

0110

R-type

10

AND

100100

and

0000

R-type

10

OR

100101

or

0001

R-type

10

slt

101010

slt

0111

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Truth table for ALUop

ALUOp1

ALUOp0

Funct

Operation (output)

XXXXXX

0010

XXXXXX

0110

XX0000

0010

XX0010

0110

XX0100

0000

XX0101

0001

XX1010

0111

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READING ASSIGNMENT
The

Processor: Datapath and Control

Read up COD Chapter 5.

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END

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