Professional Documents
Culture Documents
Computer
Architecture
Dr. Esam Al_Qaralleh
Review
computer arctecture ~ PSUT
Course Syllabus
Grading
The first priority: Maximize Learning
Your grade will depend on how much you have
learned
2 midterm exams (40% to 50%).
Quizzes and homework's (20% to 10%).
Final Exam (40%)
Activity in the class
Questions and discussion in the class give
you points and improve the quality of
teaching.
computer arctecture ~ PSUT
Course Syllabus
Text Book
Structured Computer Organization
Andrew S. Tanenbaum
Prentice-Hall, 4th Edition, 1999
Reference Books
Computer Architecture; A Quantative Approach
John L. Hennessy & David A. Patterson
Morgan Kaufmann, 3ed Edition, 2003
Computer System Architecture
M. Morris Mano
Prentice Hall, 3ed Edition, 1993
computer arctecture ~ PSUT
Course Syllabus
Class Rules
Attendance to class should be on time
Very late attendance will be count as
an absent.
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Computer Architecture
Sequential Execution
computer arctecture ~ PSUT
03/01/15
Computer Architecture
The CPU
CPU (central processing unit) is an older term for processor and
microprocessor, the central unit in a computer containing the logic
circuitry that performs the instructions of a computer's programs.
NOTABLE TYPES
- RISC: Reduced Instruction Set Computer
-Introduced in the mid 1980s
-Requires few transistors
-capable of executing only a very limited set of
instructions
- CISC: Complex Instruction Set Computer
-complex CPUs that had ever-larger sets of instructions
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MEMORY
Computers have hierarchies of memories that may be classified according to
Function, Capacity and Response Times.
-Function
"Reads" transfer information from the memory; "Writes" transfer information to
the memory:
-Random Access Memory (RAM) performs both reads and writes.
-Read-Only Memory (ROM) contains information stored at the
time of manufacture that can only be read.
-Programmable Read-Only Memory (PROM) is ROM that can be written once
at some point after manufacture.
-Capacity
bit = smallest unit of memory (value of 0 or 1);
byte = 8 bits;
In modern computers, the total memory may range from say 16 MB in a small
personal computer to several GB (gigabytes) in large supercomputers.
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More on memory
Memory Response
Memory response is characterized by two different measures:
-Access Time (also termed response time or latency) defines how
quickly the memory can respond to a read or write request.
-Memory Cycle Time refers to the minimum period between two
successive requests of the memory.
-Access times vary from about 80 ns [ns = nanosecond = 10^(-9)
seconds] for chips in small personal computers to about 10 ns or less
for the fastest chips in caches and buffers. For various reasons, the
memory cycle time is more than the speed of the memory chips (i.e.,
the length of time between successive requests is more than the 80
ns speed of the chips in a small personal computer).
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Bus Speeds
Multiple Buses with different speeds is an option or a single bus
supporting different speeds is used
In a modern PC, there may be a half dozen different Bus areas.
There is certainly a "CPU area" that still contains the CPU,
memory, and basic control logic.
There is a "High Speed I/O Device" area that is either a VESA
Local Bus (VLB) or an PCI Bus
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PERFORMANCE AND
APPLICATION CHANGE
OVER TIME
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Performance
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Standalone networked
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Application Properties to
Exploit in Computer Design
Locality in memory/IO references
Programs work on subset of instructions/data at any point in time
Both spatial and temporal locality
Parallelism
Data-level (DLP): same operation on every element of a data
sequence
Instruction-level (ILP): independent instructions within sequential
program
Thread-level (TLP): parallel tasks within one program
Multi-programming: independent programs
Pipelining
Predictability
Control-flow direction, memory references, data values
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Levels of Machines
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Computer Architecture
A modern meaning of the term computer architecture
covers three aspects of computer design:
instruction set architecture,
computer organization and
computer hardware.
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Application
Operating
System
Compiler
Memory
system
Firmware
Instruction Set
Architecture
I/O system
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RISC Architecture
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LOGO
www.themegallery.com