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Density
Complexity
Size
Of field-programmable gate arrays (FPGAs), it provides an
attractive and cost-efficient alternative to semi-custom
application specific integrated circuits (ASICs).
Standard ICs:
Customized ICs
PLDs:
a fixed architecture
The first type of PLDs considered has the AND-OR plane structure shown in
the figure.
This type of architecture is used to implement ROMs, PLAs, and PALs.
It implements Boolean expressions in Sum of Products (SOP) form:
AND plane forms product terms selectively from the inputs, and
Product Terms
Inputs
AND Plane
OR Plane
Outputs
Storage Devices
Read-Only, or
Random Access
depending on whether the contents of a memory cell
can be written during normal operation of the device.
ROM (read-only memory) is a device programmed to
hold certain contents, which remain unchanged during
operation and after power is removed from the
device.
RAM (random-access memory) in contrast its contents
can be changed during operation, and they vanish
when the power is removed.
Read-Only Memory
(ROM)
ROM Interface:
A 2n x b ROM consists of
an addressable array of
semiconductor memory
cells organized as 2n
words of b bits each.
n inputs defining
address lines.
b outputs called bit
lines.
ROM is non-volatile
memory. Its content is
preserved even if no
power is applied.
Address
Decoder
(Nonprogrammable)
AND Plane
OR Plane
Memory Array
2n x b
D(b-1)
D(i)
D(0)
b Outputs
(bit lines)
Outputs
A2
A1
A0
D3
D2
D1
D0
Two-dimensional decoding
Two-dimensional decoding
Two-dimensional decoding
ROM Applications
V = (1-2s)*[(2E)*(2M+33)-33]
7 6543210
S E
M
sign exponent mantissa
8
14
-law to
linear
decoder
14
14x14
multiplier
14
linear to
-law
encoder
Just connect the analog phone wires together and you get an analog
summing junction.
The 8-bit law PCM bytes must be converted to 14-bit linear format,
The signals then can be added,
Resulting signal must then be converted to 8-bit law PCM as in
previous example.
The ROM has 16 address inputs accommodating two 8-bit law PCM
operands.
For each pair of operand values, the corresponding ROM address
contains the pre-computed 8-bit law PCM sum.
ROM-based Designs
(Disadvantages)
For functions more than 20 inputs, a ROMbased circuit is impractical because of the
limit on ROM sizes that are available. For
example, one wouldnt build a 16-bit adder
in ROM it would require billions and billions
of bits.
CPLD
architecture:
Small number of
largish
PLDs (e.g., 36V18)
on a single chip
Programmable
interconnect between
PLDs
FPGA
architecture
Much larger number of
smaller programmable
logic blocks.
Embedded in a sea of
lots and lots
of programmable
interconnect.
CPLD families
Xilinx CPLDs
Xilinx CPLDs
In fact many of the 69 I/O pins would typically be used for inputs, in
which case even fewer outputs would be visible externally.
Note that the remaining macrocell outputs are still quite usable
internally, since they can be hooked up internally through the CPLDs
programmable interconnect.
Macrocells whose outputs are usable only internally are sometimes
called buried macrocells.
18 macrocells per FB
36 inputs per FB (partitioning challenge, but also
reason for relatively compact size of FBs)
Macrocell outputs can go to I/O cells or back into
switch matrix to be routed to this or other FBs.
1.
2.
3.
FPGAs
Xilinx launched the worlds first commercial FPGA in 1985, with the
vintage XC2000 device family.
XC3000 and XC4000 families soon followed, setting the stage for
todays Spartan and Virtex device families.
Each evolution of devices brought improvements in density,
performance, voltage levels, pin counts, and functionality.
Thus XC4000, Spartan and Spartan/XL devices have the same basic
architecture.
Timing is difficult to predict -- multiple hops vs. the fixed delay of a
CPLDs switch matrix.
But more scalable to large sizes.
FPGA specsmanship
Single-length lines,
Double-length lines, and
Long lines
In the XC4000 there is a rich set of connections between singlelength lines and the CLB inputs and outputs.
I/O blocks
Pin locking