A Survey of Spin-Transfer Torque Magnetic

Random Access Memory and Sensing Circuit

Improvements
Arielle Walker
December 5, 2014
VLSI Design Final Project

Outline

Intro to STT-MRAM

Comparison to different memory types

MRAM physics and the Magnetic Tunnel Junction

MTJ Electrical Properties

STT Switching Techniques

Integration of STT-MRAM with CMOS systems

Read/Write Circuit Schematics

Memory Architecture

Low Power and High Reliability Design Improvements

Spin-Transfer Torque MRAM

Non Volatile

Speed of SRAM

Memory density of DRAM

No degradation

Promising results to be the first universal memory system

Comparison of Different Memory Types

SRAM = good
read/write speeds,
bad cell size

DRAM = good high

memory density, bad
high power
consumption (due to
refresh cycle from
charge leak)

Flash = good nonvolatility, bad slow

write speeds and
endurance.

STT-MRAM = good
everywhere!

MRAM and Magnetic Tunnel Junction

Utilizes magnetic field direction to store binary data and reads it by exploiting
magneto-resistive properties

MTJ = building block of MRAM system

The MTJ: Two ferrous layers separated by an insulating layer

1, Low Resistance

0, High Resistance
Free Layer

Fixed Layer

Fixed layer can be either sufficiently thick or attached to an anti-ferrous layer

to avoid re-orientation

MRAM and Magnetic Tunnel Junction

Instead of traditional electronic device where information processing is

controlled by flow of charge, MRAM stores information by forcing electron spin

First layer acts as a spin-polarizer, second layer acts as a spin-filter

Together these form a spin-valve operation

Spin-polarized electrons tunnel though the insulating barrier on the nanoscale

MTJ Electrical Properties

Tunnel Magneto Resistance: The efficiency of spin-valve operation, typically several

hundred % with STT MRAM

RA Product Barrier: the resistance to the tunnel barrier, when optimized leads to
optimal TMR

MTJ in general have ~kOhm resistance and a change in voltage during switch of mV

Critical current densities required for switching

Some asymmetry seen in standard MRAM, avoided with STT-MRAM

STT-MRAM and MTJ Electrical Properties

Improved resistance hysteresis

Better properties seen with

MgO as insulator

Compared to traditional
MRAM:

Lower switching current is

needed

Simpler/smaller cell
architecture

Lower manufacturing costs

Improved scalability

Conventional MRAM vs. STT-MRAM Design

Spin-Transfer Torque Switching

Spin-Polarized Electrons exert a torque on the second ferrous layer (the filter)

Angular Momentum is only conserved if no net torque; angular momentum is changing

This net torque, if strong enough, can change the orientation of the magnetic field

The value can be computed by considering the net change in spin current
before/after the interaction

Three Ways

(1) Precessional, (2) Dynamic, (3) Thermal Agitation

STT-MRAM Integration with CMOS

Physics are fully compatible

Some manufacturability and layout constraints present a current design challenge

Current goes directly through MTJ, unlike traditional MRAM

Shared

Stacked

Parasitic current paths can accidentally

Each MTJ cell would need

sufficiently different critical
writing current. Read/write
would require multiple cycles

Flip a MTJ and lower TMR

Write and Read Circuits

Write

Read

Currents > threshold

Current < threshold

Memory Architecture: Three Ways

A) One storage bit is represented by
several complementary MTJs
Fast Speed, Good Sensing
High Area Overhead, Low
power efficiency during write
operation
B) Each storage bit is represented by
one MTJ and connected to one
reference cell

Lower Power

High Cell Array Area

C) Each storage bit has one MTJ and
each column of bits has one
reference cell
Reduced Cell Array Area
Some parasitic resistances
reduce sensing ability

Design Optimization to Overcome Reliability

Issues and Improve Power Consumption

Writing Circuit with Low Power Supply Voltage

Effectively reduced the power consumption by reducing the switching energy of a

conventional writing circuit from 6.0pJ/bit to 4.0pJ/bit.

Self-Enable Switching Circuit

Succeeded in saving even more energy, reducing the switching energy to only
1.6pJ/bit.

Improved the lifetime of the MTJ by reducing MTJ operations

Fore-Placed SA in the Read Circuit

Improved the robustness of process variation.

Writing Circuit with Low Power Supply

Voltage: Conventional Way

Writing Current depends on the

resistances of N1-N4 and supply voltage
at tend of writing branch.

A low Iwrite, which minimizes power

consumption, requires either reducing
those resistances or increasing the power
supply voltage

Standard power supply voltage is typically

at Vdda, slightly above Vdd

Writing Circuit with Low Power Supply

Voltage: Improved Way

Different column selected gates used in

read/write operations

Separates read/writing operations

completely

Reduces transistors (and resistance) from

6 to 4.

Makes the critical current density much

smaller

Allows for a lower power supply voltage

to be supplied

Self-Enable Switching Circuit

STT Switching pulse can occasionally

happen too fast to accurately record data

Exploiting this stochastic behavior to

implement into a sensing circuit to avoid
having to extend the write time

Utilizes one short write pulse

Self enable logic is 1 when different

signal, 0 when same.

If self enable is off, circuit does not

sense, even if W-enable is on, reducing
the number of cycles and saving power

Summary

STT MRAM is a promising new technology

Some manufacturing challenges currently consist, but are being actively

researched

Questions?