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1. State diagram
Moore
Mealy
0/00
Even
[0]
1
Even
[0]
1
11/0
1/11
Odd
[1]
Odd
[1]
0/1
3
Input
Even
Even
Odd
Odd
0
1
0
1
Next
State
Even
Odd
Odd
Even
Mealy
Present
Output
0
0
1
1
Moore
Present
State
Input
Even
Even
Odd
Odd
0
1
0
1
Next
State
Even
Odd
Odd
Even
Present
Output
0
1
1
0
3. State minimization
Already minimized
4. State encoding
Present
State
0
0
1
1
Input
0
1
0
1
Next
State
Present
Output
0
1
1
0
0
0
1
1
Mealy
Present
State
0
0
1
1
Assignment
Even 0
Odd 1
Moore
Input
Next
State
Present
Output
0
1
0
1
0
1
1
0
0
1
1
0
Assume D flip-flops
Next state = (present state) XOR
(present input)
Mealy
Output
Input
Output
Input
CLK
Q
Q
Current
State
CLK
8
N
Coin
Sensor
Vending
Machine
FSM
Open
Release
Mechanism
Clock
Moore machine
present
state
0
Reset
0
N
5
N
D
5
D
10
10
N+D
15
[open]
15
inputs
D
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
next
N
0
5
10
5
10
15
10
15
15
15
present
state
0
0
0
0
0
0
0
0
0
outp
10
Mealy machine
present
state
0
Reset
0
N/0
5
5
D/0
N/0
D/1
10
10
N + D/1
15
15
inputs
D
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
next
N
0
5
10
5
10
15
10
15
15
15
present
state
0
0
0
0
0
1
0
1
1
outp
11
10
15
inputs
D
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
next
N
0
5
10
5
10
15
10
15
15
15
present
state
0
0
0
0
0
0
0
0
0
next state
D1 D0
0 0
0 1
1 0
0 1
1 0
1 1
1 0
1 1
1 1
1 1
present
output
0
0
0
0
0
0
0
0
0
12
10
15
inputs
D
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
next
N
0
5
10
5
10
15
10
15
15
15
present
state
0
0
0
0
0
1
0
1
1
next state
D1 D0
0 0
0 1
1 0
0 1
1 0
1 1
1 0
1 1
1 1
1 1
present
output
0
0
0
0
0
1
0
1
1
13
Logic minimization
Q1
D1 Moore
D0
X X
N
D
Q1
D1
X X
Q0
1 1
X X
1
1
Q0
N
D
0 1
Q0
Q1
Open
0 1
1 1
X X
0
N
D
X X
1
Q0
Q1
Open
X X
D0
0 1
Q0
Mealy
Q1
N
D
Q1
1 1
Q0
14
Implementation
Moore
Mealy
15
7.24
7.23