Digital

Technology
Chapter 3
Sequential Logic

Page 3.1
Introduction
■ Those whose outputs depend on the state of
inputs and the previous state of the outputs.
■ Able to remember a logic value.
■ Several types of sequential logic circuits.
◆ flip-flops
◆ counters
◆ shift registers.

Page 3.2
Flip Flop
■ A bi-stable element.
■ Two stable states, 1 or 0.
■ Able to store a digital value.
■ Depends on the input and the previous
value stored.
■ Basic elements of a memory device in
a digital computer.
■ The outputs of Q and Q’ are
complemented to each other.
Page 3.3
Flip Flop
(Cont’d)
■ An initial value, 1 or 0, must be
assigned to the previous outputs for
deducing the final output values.
■ We usually use the symbol Qn to denote
the initial (or previous) value of the
output and Qn+1 to denote the new value
of the stable output.

Page 3.4
 S-R Flip Flop
■ The Set-Reset (S-R) flip-flop is the
simplest one.
■ Truth table of the S-R flip-flops.

Page 3.5
S-R Flip Flop
(cont’d)
■ S-R flip-flop with NOR gates:

Page 3.6
S-R Flip Flop
(cont’d)
■ S-R flip-flop with NAND gates:
S
Q

R Q

Page 3.7
S-R Flip-Flop
(cont’d)
Circuit symbols of S-R flip-flops:

S Q

R Q

Page 3.8
S-R Flip-Flop
(cont’d)
Timing diagram of the S-R flip-flops:

Page 3.9
Triggering with
Clock
Clock signal:

Positive Negative
Edge Edge

Page 3.10
Triggering with
Clock (Cont’d)
■ A flip-flop responses to the input
changes when the clock is at logical 1
is called a positive clocked (positive
level-triggered) flip-flop.
■ A negative clocked (negative level-
triggered) flip-flop responses to the
input changes when the clock is at
logical 0.

Page 3.11
Triggering with
Clock (Cont’d)
■ A flip-flop responses to the input
changes when the clock changes from
logical 0 to logical 1 is called a
positive edge-triggered flip-flop.
■ A negative edge-triggered flip-flop
responses to the input changes when
the clock changes from logical 1 to
logical 0.

Page 3.12
 Positive clocked
S-R Flip-Flop
■ Truth table and circuit symbol

S Q

Clk

R Q

Page 3.13
Positive clocked
S-R Flip-Flop
(cont’d)
Timing diagram of the positive clocked
S-R flip-flop:

Clk

Page 3.14
Negative clocked
S-R Flip-Flop

S Q

Clk

R Q

Page 3.15
 Edge-triggered S-R
Flip-Flop
Positive edge-triggered Negative edge-triggered

S Q S Q

Clk Clk

R Q R Q

Page 3.16
 Negative edge-
triggered J-K
Flip-Flop
■ Truth table and circuit symbol

J Q

Clk

K Q

Page 3.17
 J-K Flip Flop
■ Disadvantage of the S-R flip-flop:
only three cases of inputs are used.
■ The J-K flip-flop is designed to
overcome such limitation.

Page 3.18
J-K Flip Flop
(Cont’d)
■ Truth table of J-K flip-flops.

Page 3.19
J-K Flip Flop
(Cont’d)
■ Waveform of a negative edge-
triggered JK FF

Page 3.20
J-K Flip Flop
(Cont’d)
■A J-K flip-flop is always edge-
triggered; normally on the falling
edge.
■ The J-K flip-flop is probably the
most commonly used form of flip-
flop in digital electronic and control
circuits.
■ The fact that it has 2 inputs often
means that it is simpler to design the
control logic required to ensure that
it changes state properly in a circuit.
Page 3.21
 T-type Flip-Flop
Can be obtained from J-K FF by puting J = K

T Q

Page 3.22
 Positive edge-
triggered T-type
Flip-Flop
■ Truth table and circuit symbol

T Q

Clk

Page 3.23
 D-type Flip-Flop
■ Can be obtained from J-K FF by puting K = J’
■ Or, from S-R FF by puting R = S’

D Q

Page 3.24
 Direct inputs
■ Direct inputs allow the users to assign
the state of a flip-flop directly without
going through the normal inputs.
■ An example: a negative edge-triggered
PS
J-K flip-flop with direct preset and
J Q clear inputs.
Clk ■ Q will be set to logical 1 if PS, preset,
K Q
is 0. If Clr, clear, is 0, Q output will
Clr
be reset to 0, i.e. Low activated.
Page 3.25
Counters
■ Used for the control of sequence and
program execution.
■ Two categories of counters:
asynchronous and synchronous.
■ The asynchronous counters produce
the outputs in sequence
■ The outputs of the synchronous
counters are available at the same
time.

Page 3.26
 Counters
(Cont’d)
■ Counters are made with either J-K or
T-type flip-flops.
1 J Q

Clk
K Q

Page 3.27
Counters
(Cont’d)
■ Q produces one pulse for every two
clock pulses input.
■ The counter counts once for every two
clock pulses.
■ The frequency at Q is half of that at
the clock.
■ Sometimes called a divider.
■ A J-K flip-flop can be regarded as a
divide-by-2 counter.

Page 3.28
 Divide-by-16
Ripple
(Asynchronous)
Counter
Q0 Q1 Q2 Q3

1 J0 Q0 1 J1 Q1 1 J2 Q2 1 J3 Q3

Clock Clk Clk Clk Clk

1 K0 1 K1 1 K2 1 K3
FF0 FF1 FF2 FF3

Page 3.29
 Divide-by-16
Ripple Counter
(Cont’d)
Clock

Q0

Q1

Q2

Q3

Page 3.30
Divide-by-16
Ripple Counter
(Cont’d)
■ Q0 produces one clock pulse for every
two input clocks.
■ At Q3, only one clock pulse is
generated for every 16 input clocks.
■ The output sequence in Q3, Q2, Q1
and Q0, forms the binary numbers
from 0 to 15
■ It counts the binary numbers.

Page 3.31
Divide-by-16
Ripple Counter
(Cont’d)
■ Propagation delay happens in
operations of flip-flops.
■ Time delay for all output clocks
compared with their input clocks.
■ Outputs are not available at the same
time, it is an asynchronous counter.

Page 3.32
Divide-by-16
Synchronous
Counter
■ All output clock transitions happen at
the same time.
■ Clocks are connected together.
■ Input connections are more
complicated.

Page 3.33
Divide-by-16
Synchronous
Counter (Cont’d)

Page 3.34
Divide-by-16
Synchronous
Counter (Cont’d)
■ FF0 is configured to change output
state for every transition of the clock.
■ FF1 changes output state when the
output of FF0 is 1.
■ When both Q0 and Q1 are at logical 1,
the output FF2 changes state after the
clock.
■ FF3 changes state after the clock pulse
when all other outputs are at logical 1.

Page 3.35
Shift Registers
■ Store a vector of binary digits - a simple
memory array.
■ Serial input method shifts the data into the
shift register one bit by one bit.
■ Right-shift: LSB first, MSB last.
■ Left-shift:MSB first, LSB last.
■ Parallel input method: stores the data into the
register all at a time.
■ The data in the shift register can be retrieved
either in series or in parallel.
Page 3.36
Serial In – Serial
Out

Page 3.37
Serial In–
Parellel Out

Page 3.38
Parellel In –
Parellel Out

Page 3.39
Parellel In –
Serial Out

Page 3.40