ARM System Architecture

Sandeep Srivastava

Sandeep Srivastava

Introduction to ARM
Architecture
ARM is a 32-bit RISC architecture that has some
CISC features
So it is not a pure RISC Architecture though for
most purposes it can be considered as one
It also has a 16 bit extension called Thumb
which has a smaller instruction but runs faster
ARM9 standard does not give any instructions
on how the underlying implementation is done,
it only has the high level description of the
hardware architecture and the Instruction Set
Architecture(ISA)
Sandeep Srivastava

Introduction
ARM is a pipelined architecture. Different
versions of ARM have different no. of
stages in the pipeline, viz. ARM7 has a 3stage pipeline, ARM9 has a 5 stage pipeline
and ARM11 has a 7 stage pipeline.
With time, ARM has evolved and various
versions called Family have been
introduced, such as ARM7 Family, ARM9
Family, ARM10 Family and ARM11 Family
We are mostly concerned with ARM9 Family
Sandeep Srivastava

ARM Features
As already mentioned, ARM9 has a 5-stage
pipeline. A brief introduction of pipelining follows
ARM9 has an in-line Barrel Shifter which
conditionally shifts one of the two operands
before passing them to the ALU
It has 3 types of interrupts, viz. Interrupt
Request(IRQ), Fast Interrupt Request(FIQ) and
Software interrupt(SWI)
ARM9 can operate in different modes, such as
User, IRQ, FIQ, supervisory, etc.
ARM is a load-store architecture
Sandeep Srivastava

Pipelining
Pipelining is a method of running the
processor faster by dividing each
instruction into several stages.
While one instruction has completed
one stage, it is passed to the second
stage and the next instruction in
sequence is sent into the first stage

Sandeep Srivastava

Pipelining: An assembly line for

mobile phones
The manufacturing of a mobile phone handset
can be composed of the following stages:
Time=
1
Phone
1

Phone
2

Phone
3

Mounting the
chips on PCB

Time=
2

Time=
3

Adding the visual

screen and keyboard

Mounting the
chips on PCB

Assembling the
battery and
body

Adding the visual

screen and keyboard

Mounting the
chips on PCB

Sandeep Srivastava

Time=
4

Time=
5

Finished
Product

Assembling the
battery and
body

Adding the visual

screen and keyboard

Finished
Product

Assembling the
battery and
body

Pipelining
The ARM9 processor processes the
instruction in five stages Instruction
Fetch(IF), Instruction Decode(ID),
Execute(EX), Memory Access(MEM)
and Write Back(WB)

Sandeep Srivastava

Pipelining
The pipeline can be seen as a series of datapaths
CLOCK
ALU

IM

Re
g

DM

time

Re
g

ALU

IM

Re
g

DM

Re
g

ALU

IM

Re
g
IM

DM
Re
g

Sandeep Srivastava

Re
g
DM

Re
g

Barrel Shifter
ARM architecture includes a Barrel
Shifter that conditionally shifts one of
the operands before passing them to
the ALU
This is a very powerful feature of
ARM9, like 5-stage pipelining
Arithmetic , logic and other
instructions can take an additional
specification to shift one of the
operands:
Sandeep Srivastava

Barrel Shifter
PRE
r5 = 3
r7 = 5

Instr. : MOV r7, r5, LSL #2 ; let r7 = r5*4

= (r5 << 2)

POST
r5 = 3
r7 = 12

Sandeep Srivastava

ARM Core Dataflow Model showing

the Barrel Shifter

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Conditional Execution
ARM 9 allows a specification in the
instruction to execute or not execute
the instruction based on the value of
a flag like z(zero), c(carry), etc.
This saves the programmer from
executing conditional branches such
as BZ and makes the instruction run
faster, for example
Instr.: ADDEQ r1, r1, r2
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ARM9 as a RISC
ARM9 implements the RISC design philosophy in 4
main ways:
1. Instructions: RISC follows the idea of shorter
and fewer instructions than CISC so that these
instructions can be executed at the average rate of
one clock cycle. RISC instructions are all of the
same length. Contrary to this, CISC instructions
typically take variable clock cycle to execute and
are of variable length. Thus RISC puts the burden
on the programmer by making the software more
complex, whereas CISC makes the hardware more
complex
Sandeep Srivastava

ARM9 as a RISC
2. Pipelining As already introduced,
pipelining breaks each instruction into 5 stages
and ideally the processor can complete 1
instruction per clock cycle. There is no need for
an instruction to be run by a miniprogram
called microcode as in CISC processors
3. Registers RISC processors have a large
number of registers which can be used by
instructions as desired. In contrast, CISC
processors typically have registers dedicated
to a particular task
Sandeep Srivastava

ARM9 as a RISC
4. Load-Store Architecture : The
processor executes instructions on
data held in registers. The registers
act as a fast memory(faster than
cache) close to the ALU. Separate
instructions load and store data from
registers to and from memory. By
contrast, CISC processors often
operate directly on data held in
memory which takes longer
Sandeep Srivastava