Silicon on Insulator (SOI)

Based Devices Part 2

Amitava DasGupta
Department of Electrical Engineering
I.I.T. Madras
Chennai 600037
adg@ee.iitm.ac.in
1

Short channel effect (SCE) in SOI

Bulk
S

Qd1

Qd1

Qd1

SOI
S

Qd1
Buried oxide

B uried
oxide

Charge sharing due to source and drain is less in FD SOI

2

Threshold Voltage variation

FDSOI vs. Bulk (and PDSOI)
ThresholdVoltage(V)

1.2
1.0
0.8

Bulk,Model
TFSOI,Model
Bulk,Experiment
TFSOI,Experiment

0.6
0.4
0.2
0.0
0.0

0.5

1.0

1.5

EffectiveChannelLength(m)

2.0

SCE due to fringing fields in the BOX

Electric field in the BOX due to S/D depletion charge

tends to terminate in the silicon film rather than substrate
This induces inversion charge at the back surface and
degrades subthreshold characteristics

Fringing Fields in SOI

Possible solutions

Thinning of BOX But this results in

Increase in effective body capacitance and subthreshold slope
Increase in source drain junction capacitance
(Solution Use Silicon-on-Nothing (SON) ?)
5

Dynamic Threshold MOSFET

When device is ON (VGS is high)
When VGS = VDD,

I on VDD VTh

For higher current drive (higher speed), VTh

should be low

When device is OFF (VGS is low)

I off
When VGS = 0,

Vth

exp
nVt

For low leakage current (low static power

dissipation), VTh should be high
VTh should reduce with increase in VGS

Dynamic Threshold MOSFET

(PD SOI)
Achieved by tying
Gate and Body

VTh VTho 2 B VSB 2 B

Since VSB = -VGS

VTh VTho 2 B 2 B VGS

With increase in VGS,

VTh reduces
Disadvantage : VGS cannot exceed 0.6V

Dynamic Threshold MOSFET

(FD SOI)
TBOX= 5 nm
TBOX= 10 nm
TBOX= 20 nm
TBOX= 30 nm
TBOX= 40 nm

0.4

n+

0.3

VTHF

n+

-3

Na=4.2e17 cm
TFox=5 nm
TSi=50 nm
VFBF=VFBB=-1 V

0.2

0.1
-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

VGB (V)

As VGS increases, VTh reduces

Advantage over PDSOI : VGS is not limited to 0.6V
Disadvantage : Substrate is common to all devices in chip So
special scheme for isolation of substrate is necessary

Why Double Gate (DG) MOSFETs?

Short channel effects
(SCE) in MOSFETs are
due to field penetration
from drain to source
Due to SCE, gate has
less control of channel,
resulting in
Lower VTh (Threshold
Voltage)
Higher S (Subthreshold
swing)

To reduce SCE, the

channel doping conc. (NA)
has to be increased
9

Why Double Gate (DG) MOSFETs? (contd.)

For gate length (L) of 50nm,
required NA is above 1018/cm3
Problems
For NA > 1018/cm3, carrier mobility
is very low
When L = 10 nm, channel volume
~ 10-18 cm3 , resulting in severe VTh
variations due to random
fluctuation of dopant atoms

Solution Use DG MOSFET

It does not require channel doping
for SCE control
A second gate and a fully depleted
silicon film enhances the control of
gate
The SOI film is undoped or lightly
doped to ensure full depletion
For better SCE control, both gate
oxide thicknesses (tox) are equally
small and VG1 = VG2

10

Subthreshold Swing in DG MOSFETS

For long channel devices
Effect of S/D can be ignored
Since SOI film is fully depleted
and mobile charge conc. is
negligible in subthreshold
region, there is one-to-one
correspondence between VG and

channel potential

For short channel devices

Effect of S/D cannot be ignored
To suppress SCE, electrical
distance of the channel centre to
the gates must be much smaller
than half the channel length
11

Threshold Voltage of DG
MOSFETS
Since the silicon film is undoped
it is virtually equipotential across
the thickness
results in volume inversion
Popular definition of VTh (surface
potential equal to 2B) cannot be
used
Alternate definition :Gate voltage
when inversion charge density
reaches a particular value (QTh)
QTh = 3.24 1010 /cm2
2 2
q

Poissons equation:

n
e
i
2
2

Si

12

Threshold Voltage of DG MOSFETS (contd.)

for long channel devices depends on the

metal and silicon thickness
Th

Threshold voltage shift reduces for smaller silicon

13
thickness

Logic Circuit using DG MOSFETs

NAND

NOR

PMOS turns ON
when any input is
LOW

NMOS turns ON
when any input
is HIGH

Separate gate
biasing in DG device
provides variable
threshold voltage
Independent front
and back gate bias
reduces the number
of transistors for
implementing logic
functions

M. Chiang, et al, Novel high-density low-power logic circuit techniques using DG devices,
14
IEEE Trans. Electron Devices, vol. 52, pp. 2339-2342, Oct. 2005

Scaling Limits
Criterion
S = 70 mV / decade (excellent)
S = 100 mV / decade (moderate)
VTh < 100V
If L changes by 30% due to
process variation, VTh should
change by less than 7% of supply
voltage

Results assuming tsi = 3 nm (onset

of quantization effects) and tox =
0.9 nm (limited by direct tunneling)
L can be reduced to 7 nm for S =
100 mV / decade
L can be reduced to 12 nm for S =
70 mV / decade
Applying VTh < 100V, L can be
reduced to 12 nm
Applying process variation
condition, L can be reduced to only
16 nm
15

Ultra Thin DG SOI MOSFET

Carrier confinement in very
narrow potential wells is
governed by the wave
functions and energy levels of
the various subbands.
Self consistent solution of
Schrdinger and Poissons
equation is now necessary to
calculate carrier
concentrations
The striking feature obtained
by this solution is that most of
the carriers flow through the
middle of the film, and not at
the interfaces
16

Ultra Thin DG SOI MOSFET

Interesting result
The transconductance of
DG SOI is more than
double SG SOI
Why ?

Most of carriers in DGSOI

flow through the middle of
the film, where the carrier
mobility is much higher
than at the interfaces

17

Gate leakage current in DGSOI

Since the carrier
concentration peak is
away from the interface,
gate leakage current in
Ultra-thin DGSOI is less
than bulk MOSFETS
This advantage is more
pronounced for high-K
dielectrics
This allows the use of
thinner gate dielectrics
leading to more
aggressive scaling
18

Multiple Gate SOI MOSFETs

1) Single Gate
2) Double Gate
3) Triple Gate
4) Quadruple Gate
5) Pi-Gate

Pi-Gate Fabrication steps

Increasing the number of gates increases gate control and

reduces SCE and subthreshold slope
The Pi-gate has the advantages of quadruple gate, but is
much easier to fabricate
J.T. Park and J.P. Colinge, Multiple-Gate SOI MOSFETs: Device design guidelines,
IEEE Trans. Electron Devices, vol. 49, pp. 2222-2228, Dec. 2002

19

Special Triple Gate Device - FINFET

Relatively simple process

Effective channel width (W) = 2 x Hfin + Tfin
W can be increased by having multiple fins
Devices with L = 18 nm and tox = 2.5 nm have been demonstrated
Empirical scaling rule to suppress SCE L > 3Tfin

20

Evolution of FinFET
t

ox1

G ate
S i f ilm

ox1

si

ox2

G ate
S i f ilm

ox2

substrate

si

G ate

Double Gate MOS

Conventional SOI MOS

t
t

ox1
ox2

G ate
S i f ilm
G ate

Ultra thin body

Double Gate MOS

t
si

ox1
ox2

G ate
S i f ilm

G ate

FinFET
21

si

Evolution of FinFET
t

ox1

G ate
S i f ilm

t
t

si

ox2

ox1

G ate
S i f ilm

ox2

si

G ate

Double Gate MOS

substrate

Conventional SOI MOS

t
t

ox1
ox2

G ate
S i f ilm

si

G ate

Ultra thin body

Double Gate MOS

FinFET
22

Evolution of FinFET
t

ox1

G ate
S i f ilm

t
t

si

ox2

substrate

ox1

G ate
S i f ilm

ox2

si

G ate

Double Gate MOS

Conventional SOI MOS

S i f ilm

si

G ate

ox2

G ate

S i f ilm

ox1

G ate

G ate

Ultra thin body

Double Gate MOS

FinFET
23

Evolution of FinFET
t

ox1

G ate
S i f ilm

t
t

si

ox2

ox1

G ate
S i f ilm

ox2

si

G ate

Double Gate MOS

substrate

Conventional SOI MOS

S i f ilm

si

G ate

ox2

G ate

S i f ilm

ox1

G ate

G ate

Ultra thin body

Double Gate MOS
FinFET
24

Evolution of FinFET
t

ox1

G ate
S i f ilm

t
t

si

ox2

ox1

G ate
t

S i f ilm
ox2

si

G ate

Double Gate MOS

substrate

Conventional SOI MOS

S i f ilm
G ate

G a te

ox2

G ate

S i f ilm

ox1

G a te

si

BOX

Ultra thin body

Double Gate MOS
FinFET (Double
or Triple Gate)

25

Summary
SOI MOS devices have several inherent advantages
over conventional bulk MOS devices
Till recently, development of SOI CMOS was hampered
by the non-availability of good quality SOI wafers.
Modern techniques have improved the quality of these
wafers
PD SOI are similar to Bulk SOI. However, absence of
substrate contact results in Floating Body Effects
FD SOI devices with Ultra thin Body (UTB) have several
advantages over PD SOI/Bulk MOSFETs
FD SOI devices have evolved into Multiple Gate FETs
(MuGFETs) , which may be devices of future
There is lot of scope of modelling these devices
26

Thank you

27