Lecture 2

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Instruction Set
Instruction Words of a computer language
Instruction set Collection of instructions
Different computers have different instruction sets
But they have many aspects in common
MIPS (Microprocessor without Interlocked Pipeline
Stages) architecture RISC architecture developed by
MIPS technologies

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Arithmetic Operations
Consider the notation,
add a, b, c
This adds the two variables b & c & puts the sum in a
All arithmetic operations are of this form
Perform only one operation
Must have exactly three variables

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 If we want to place the sum of variables b, c, d & e into

variable a, the following sequence of instructions are given
add a, b, c
add a, a, d
add a, a, e

Hardware for a fixed no.of operands is simpler than the

hardware for a variable no.of operands.

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 Design Principle 1 Simplicity favors regularity

Regularity makes implementation simpler
Simplicity enables higher performance at lower
cost

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Compiling C statements into MIPS

Consider the C statements,
a = b + c;
d = a e;
Equivalent MIPS instructions are,
add a, b, c
sub d, a, e

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 Consider the complex C statement,

f = (g + h) (i + j);
Equivalent MIPS instructions are,
add t0, g, h
add t1, i, j
sub f, t0, t1

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Register Operands
Arithmetic instructions use register operands
MIPS has 32 X 32-bit registers
Used for frequently accessed data
Numbered from 0 to 31
32-bit data --- Word
Design Principle 2 Smaller is faster
Main memory has millions of locations

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 MIPS convention For registers, use two-character

names preceded by a dollar sign
For eg, $s0, $s1 etc for registers that correspond to high
level language variables & $t0, $t1 etc for temporary
registers needed to compile the program into MIPS
instructions

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Compiling using Registers

Consider the statement,
f = (g + h) (i + j);
Variables f , g, h, i & j are assigned to the registers $s0,
$s1, $s2, $s3 & $s4 respectively
Equivalent MIPS instructions are,
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
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Memory Operands
Main memory is used for complex data structures like
arrays, structures etc
To perform arithmetic operations
Load values from memory to registers
Store result from register to memory
Memory is a large single dimensional array & is byte
addressed
Each address identifies an 8-bit byte
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 MIPS is big-endian Most significant byte is at least

address of a word
Load instruction
Copies data from memory to a register
MIPS instruction is lw (load word)
Format is, operation name followed by the register
to be loaded, then a constant (offset) & register used
to access memory (base register)
Sum of constant portion & contents of second
register forms the memory address
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Compiling Memory Operands

Assume A is an array of 100 words. Consider the
statement,
g = h + A[8];
g in $s1, h in $s2 & base address of A in $s3
Equivalent MIPS instructions are,
lw $t0, 32($s3) #t0 gets A[8]
add $s1, $s2, $t0

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 Store instruction
Copies data from a register to memory
MIPS instruction is sw (store word)
Format is, operation name followed by the register
to be stored, then offset to select the array element &
the base register

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Compiling using Load & Store

Assume h is associated with register $s2 & base address
of A is in $s3. Consider the statement,
A[12] = h + A[8];
Equivalent MIPS instructions are,
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 48($s3)

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Registers Vs Memory
Registers are faster to access than memory
Keep the most frequently used variables in
registers
Memory operations require load & store
More instructions to be executed

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Immediate Operands
Constant data specified in an instruction
MIPS instruction is addi (add immediate)
To add constant 4 to register $s3 we write,
addi $s3, $s3, 4

No subtract immediate instruction. For this, use a

negative constant
addi $s2, $s1, -2

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 Design Principle 3 Make the common case fast

Constant operands occur frequently
Immediate operands avoid a load instruction

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The Constant Zero

MIPS register 0 ($zero) is the constant 0
Cannot be overwritten
Used to move values between registers
add $t2, $s1, $zero

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Representing Instructions in the Computer

Base 2 numbering is used in computer hardware
In MIPS register names are mapped into numbers as
follows: Registers $s0 to $s7 map onto 16 to 23
Registers $t0 to $t7 map onto 8 to 15

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MIPS Instruction format

R-type format For register operand instructions
6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

op

rs

rt

rd

shamt

funct

op Operation code (opcode)

rs First register source operand
rt - Second register source operand
rd Register destination operand
shamt Shift amount (Zero for now)
funct Function code (Extends opcode)
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 For eg, add $t0, $s2, $t0

Machine language version is,

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op

rs

rt

rd

18

shamt funct
0

32

2
3

 I-type format For immediate operand & data transfer

instructions

For

6 bits

5 bits

5 bits

op

rs

rt

16 bits
constant

eg, addi $s1, $s2, 100

Machine language version is,

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op

rs

rt

18

17

constant
100

2
4

 For eg, lw $s1, 100($s2)

Machine language version is,

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op

rs

rt

35

18

17

constant
100

2
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 Design Principle 4 Good design demands good

compromises
Keep all instructions the same length
Different
instructions

instruction

formats

for

different

Different formats complicate hardware, but try to

keep the formats similar

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MIPS Instruction Encoding

Instruction

Format

op

rs

rt

rd

add

reg reg

reg

32

NA

sub

reg reg

reg

34

NA

addi

reg reg NA

NA

NA

Constant

lw

35

reg reg NA

NA

NA

Address

sw

43

reg reg NA

NA

NA

Address

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shamt funct

address

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Logical Operations

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Operation

MIPS instruction

Shift left logical

sll

Shift right logical

srl

Bit-by-bit AND

and, andi

Bit-by-bit OR

or, ori

Bit-by-bit NOT

nor

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 Instruction format
op

rs

rt

rd

shamt

funct

Shift left logical (sll)

Shift left & fill with 0 bits
sll by i bits means multiply by 2i
Eg:- sll $t2, $s0, 4

#$t2 = $s0 << 4 bits

Machine language version is,

0

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16

10

2
7

 Instruction format
op

rs

rt

rd

shamt

funct

Shift right logical (srl)

Shift right & fill with 0 bits
srl by i bits means divide by 2i
Eg:- srl $t2, $s0, 4

#$t2 = $s0 >> 4 bits

Machine language version is,

0

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16

10

2
7

 AND operation
Bit-by-bit operation
Leaves a 1 if both operand bits are 1
For eg, and $s1, $s2, $s3
Machine language version is,
op
rs
rt
rd shamt funct
0

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18

19

17

36

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 OR operation
Bit-by-bit operation
Leaves a 1 if either operand bit is 1
For eg, or $s1, $s2, $s3
Machine language version is,
op
rs
rt
rd shamt funct
0

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18

19

17

37

2
8

 NOT operation
Bit-by-bit operation
Inverts the bit value
MIPS has NOR 3-operand instruction
a NOR b = NOT (a OR b)
For eg, nor $s1, $s2, $s3
Machine language version is,
op
rs
rt
rd shamt funct
0
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18

19

17

39
2
8

 and $t0, $t1, $t2

$t2

0000 0000 0000 0000 0000 1101 1100 0000

$t1

0000 0000 0000 0000 0011 1100 0000 0000

$t0

0000 0000 0000 0000 0000 1100 0000 0000

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 or $t0, $t1, $t2

$t2

0000 0000 0000 0000 0000 1101 1100 0000

$t1

0000 0000 0000 0000 0011 1100 0000 0000

$t0

0000 0000 0000 0000 0011 1101 1100 0000

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 nor $t0, $t1, $zero

$t1

0000 0000 0000 0000 0011 1100 0000 0000

$t0

1111 1111 1111 1111 1100 0011 1111 1111

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Decision Making Instructions

Conditional branch

Branch to a labeled instruction if a condition is true

Else continue sequentially
Instructions in MIPS
Branch if equal (beq)
Branch if not equal (bne)
Unconditional branch
MIPS instruction is jump (j)
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 beq reg1, reg2, L1

Go to the statement labeled L1 if the value in reg1
equals the value in reg2
bne reg1, reg2, L1
Go to the statement labeled L1 if the value in reg1
is not equal to the value in reg2
j L1
Unconditional jump to the statement labeled L1
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Compiling if statements
Consider the statement,
if (i == j) f = g + h; else f = g h;
Assume that variables f through j correspond to registers
$s0 through $s4
Compiled MIPS code is,
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit:
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Compiling loop statements

Consider the statement,
while (save[i] == k) i += 1;
Assume that i & k correspond to registers $s3 & $s5 & the
base of array, save, is in $s6
Compiled MIPS code is,
Loop: sll $t1, $s3, 2
add $t1, $t1, $s6
lw $t0, 0($t1)
bne $t0, $s5, Exit
addi $s3, $s3, 1
j Loop
Exit:
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# $t1 = 4 * i
# $t1 = addr of save[i]
# $t0 = save[i]
# if save[i] k, exit
# i = i +1
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 Instruction format for branch instruction

6 bits

op

5 bits

5 bits

16 bits

rs

rt

constant/address

For eg, beq $s1, $s2, L1

Machine language version is,

4

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17

18

25

4
0

 Instruction format for jump instruction

6 bits

op

26 bits

constant/address

For eg, j L2

Machine language version is,

2

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2500

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Decision Making Instructions (contd)

Two more jump instructions are present
i.

Jump & link (jal)

Eg: jal L1 Jump to the label & simultaneously
save the address of the following instruction in
$ra
Machine language version is,
op
3

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constant
2500
4
2

ii. Jump register (jr)

Eg: jr $ra Jump to the address stored in $ra
Machine language version is,

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op

rs

rt

rd

31

shamt funct
0

4
3

 Set on less than (slt)

Compares two registers & sets a third register to 1
if the first is less than second, else set it to 0

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slt $t0, $s3, $s4

# $t0 = 1 if $s3 < $s4

slti $t0, $s2, 10

# $t0 = 1 if $s2 < 10

4
4

 Instruction format
op

rs

rt

rd

shamt

funct

For eg, slt $s1, $s2, $s3

Machine language version is,
op
0

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rs
18

rt

rd
19

17

shamt
0

funct
42

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MIPS addressing for 32-bit Immediate Operands

Generally constants are short & fit into the 16-bit field
For 32-bit constants MIPS has load upper immediate (lui)
instruction
Set the upper 16 bits of a constant in a register
Allows a subsequent instruction to specify the lower 16
bits of the constant

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 lui $t0, 255

Machine language version of above instruction
15

255

Contents of $t0 after executing the instruction

255

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 Load the following 32-bit constant into register $s0

0000 0000 0011 1101 0000 1001 0000 0000
First load upper 16 bits as, lui $s0, 61
Now $s0 is,
0000 0000 0011 1101 0000 0000 0000 0000
Add the lower 16 bits as, ori $s0, $s0, 2304
Now $s0 is,
0000 0000 0011 1101 0000 1001 0000 0000
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MIPS Register Conventions

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Name

Register No

Usage

$zero

Constant 0

$at

Assembler

$v0-$v1

2-3

Values for results

$a0-$a3

4-7

Arguments

$t0-$t7

8-15

Temporaries

$s0-$s7

16-23

Saved

$t8-$t9

24-25

Temporaries

$k0-$k1

26-27

Kernel

$gp

28

Global pointer

$sp

29

Stack pointer

$fp

30

Frame pointer

$ra

31

Return address
4
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 Addressing modes Multiple forms of addressing

Register addressing Operand is a register
Eg: add, sub, and, jr
Base or displacement addressing Operand is at the
memory location whose address is the sum of a register
& a constant in the instruction
Eg: lw, sw
Immediate addressing Operand is a constant within
the instruction
Eg: andi, ori

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 PC-relative addressing Address is the sum of the

program counter (PC) & a constant in the instruction
Eg: beq, bne
Pseudo direct addressing Address is the 26 bits in the
instruction concatenated with the upper 4 bits of
program counter
Eg: j, jal

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