UNIT II

Control Unit

Mrs.Rajani.P.K
06/21/15

Control Unit
Single us organization - register transfer,
performing an arithmetic or logic operation,
fetching and storing word from/to memory,
execution of complete instruction , branch
instruction, Multi bus organization, hardware
control design methods state table and
delay element method
A complete processor, Micro-programmed
control microinstructions, micro-program
sequencing, wide branch addressing, microinstructions with next address field, perfecting
microinstructions, emulation

Objectives
To study Single and Multi Bus Organization
Execution of an instruction by generating control
signals
To design control unit
Hardwired Controlled Design
State Table method
Delay Element method

REFERENCE
Book: Computer organization by Hamacher
Chapter 7
Pg 411

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TOPICS TO COVER
Chapter 7: Basic Processing Unit
Single Bus Organization
Register Transfer
Performing an arithmetic or logic operation
Fetching and storing word from/to memory

Execution of complete instruction

branch instruction

Multi-bus Organization
Hardwired Control:
Design methods State table and classical method
A complete Processor

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- Continued..
Micro-programmed Control

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Microinstructions
micro- program sequencing
wide branch addressing
microinstructions with next address field
perfecting microinstructions
Emulation.

Recap: Organisation
Bus

Processor

Memory

Control
Cache
Datapath
Registers

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Devices
Input
Output

Fundamental Concepts
Processor (CPU): the active part of the computer,

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which does all the work (data manipulation and

decision-making).
Datapath: portion of the processor which contains
hardware necessary to perform all operations
required by the computer.
Control: portion of the processor (also in hardware)
which tells the datapath what needs to be done (the
brain).

Fundamental Concepts (2)

Instruction execution
cycle: fetch, decode,
execute.
Fetch: fetch next

instruction (using PC)

from memory into IR.
Decode: decode the
instruction.
Execute: execute
instruction.

Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction

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Processor
Processing unit [Instruction Set ProcessorISP] or Processor:
executes machine instructions and
coordinates the activities of the other units.
It used to be called Central Processing
Unit(CPU).
Central is less appropriate today since
modern computers include several
processing units.
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 Assume each word is 4 bytes and each instruction is

stored in a word, and that the memory is byte
addressable.
To execute an instruction, the processor has to perform
the following 3 steps:
1.Fetch the contents of the memory location pointed to by
the PC.The contents of this location are interpreted as
an instruction to be executed.Hence, they are loaded
into Instruction Register(IR).
Symbollically, this can be written as,
IR [[PC]]
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2.Assuming that the memory is byte

addressable, increment the contents of
the PC by 4, that is,
PC [PC] + 4
3. Carry out the actions specified by the
instruction in the IR.
*In cases where an instruction occupies more than one word, steps1

&2 must be repeated as many times as necessary to fetch the

complete instruction.
steps1 &2-Fetch phase
step3-Execution phase

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Single-bus Organization (p413)

Internal
processor bus

Address line
Memory
bus
Data line

PC

Control signals
...

MAR

Instruction
decoder
and control
logic

MDR

IR

Y
Constant 4

RO
MUX

Select
ALU
control
lines

Add
Sub

ALU
Carry-in

XOR

TEMP
Z

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:
:
R(n1)

Single-bus Organization
Instructions can be executed by performing one or more of
the following operations:
Register Transfer
Transfer a word of data from one processor register to another or
to the ALU.

Performing ALU operation

Perform arithmetic or logic operation and store the result in a
processor register.

Fetching word from memory

Fetch the contents of the given memory location and load them
into a processor register.

Storing word to memory.

Store a word of data from a processor register into a given
memory location.
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Multiple-Bus Organization
Bus A Bus B

Bus C

Bus A Bus B

Bus C

Incrementer
Instruction
decoder

PC

IR

Register
file

MUX

Constant 4

MDR
A

ALU
R

MAR

Address
line
Memory bus
data lines
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Instruction Execution
An instruction can be executed by performing one or more of the

following operations in some specified sequence:

Transfer a word of data from one register to another or to the ALU
(Arithmetic Logic Unit).
Perform an arithmetic or a logic operation and store the result in a
register.
Fetch the contents of a given memory location and load them into a
register.
Store a word of data from a register into a given memory location.

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Register Transfer

(p415)

Register to register transfer:

For each register Ri, two control signals:
Riin used to load the data on the bus into the register.
Riout to place the registers contents on the bus.

Example: To transfer contents of R1 to R4:

Set R1out to 1. This places contents of R1 on the bus.
Set R4in to 1. This loads data from the processor bus into R4.

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Register Transfer (2)

Internal
processor bus
Ri in

Y in
X

Ri

Y
Constant 4
Select

X
Ri out

MUX
A

ALU
Z in

X
Z
X
Z out

I/P and O/P gating for registers

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All operations & data transfers takes place within time periods called
PROCESSOR CLOCK.

When e two or more clock signals may be needed to

guarantee proper transfer of data, that is known as
Mutiphase clocking.

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I/P and O/P gating of

1 register bit

When Rin=1, MUX selects data on the bus. This data will be loaded into F/F
at rising edge of clk.
When Rin=0, MUX feeds back the value currently stored in F/F.
Q O/P is connected to bus via tri-state gate.
When Riout=0, gates o/p -> high impedence
When Riout=1, gates drives bus to value 0 or 1
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Arithmetic/Logic Operation(Pg 415)

Internal
processor
bus

ALU: Performs arithmetic

and logic operations on its
A and B inputs.
A sequences of operation
to add the contents of R1
to R2& store in R3 is:
To perform
R3 [R1] + [R2]:
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in

Y in

Ri

Constant
4

X
Ri out

MUX
A

ALU
Z in

X
Z
X
Z out

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Select

Ri in

STEP 1:
Reg R1 o/p and Reg Y I/P are enable

So R1 contents transferred to Y over the bus

STEP 2:
MUX select signal set to SelectY
So MUX gates the Y contents to I/p A of ALU
At same time-> Contents of R2 are gated onto the bus and hence,
to I/P B of ALU
Here ADD line is set to 1. SO ALU O/P = A+B -> Then o/p into Z
STEP 3:
Contents of Z transferred to Destination Reg R3.

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Fetching a Word from Memory (Pg418)

GENERAL OPERATION:
Processor has to specify address of memory location
Also need to Request a read operation
Data might be-> instruction/ operand
1. Processor transfers required addr to MAR
2. MAR O/P connected to addr line of mem bus
3. At same time, Processor uses control signals of mem bus to indicate
that read operation is needed.
4. When requested data is received from mem , they are stored in
MDR.
5. From MDR, can be transferred to other reg in processor.

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 MDR CONNECTIONS

MDR has four control signals:

MDRin, MDRout, -> to control connection to internal bus

MDRinE and MDRoutE .-> to control connection to exterrnal bus

Memory-bus data
lines

Internal processor
bus

MDR inE

MDR in

X
MDR

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MDR outE

MDR out

Fetching a Word from

Memory (Pg418)
Move (R1), R2

/* R2 [[R1]]

1. MAR [R1]
2. Start a Read operation on the memory bus
3. Wait for the control signal MFC(Memory Function completed)
response from the memory
4. Load MDR from the memory bus
5. R2 [MDR]

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Reading a Word from Memory (2)

Move (R1), R2 /* R2 [[R1]]
Sequence of control steps:
1. R1out, MARin, Read
2. MDRinE, WMFC
3. MDRout, R2in

WMFC: Wait for arrival of MFC (Memory-FunctionCompleted) signal.

MFC: To accommodate variability in response time,

the processor waits until it receives an indication that
the Read/Write operation has been completed. The
addressed device sets MFC to 1 to indicate this.
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Storing a Word in Memory

Move R2, (R1) /* [R1] [R2]
Sequence of control steps:
1. R1out, MARin
2. R2out, MDRin, Write
3. MDRoutE, WMFC
STEPS:
1. Desired addr is loaded into MAR
2. Data to be written are loaded into MDR & write command is issued
3. Processor remains in step 3 until mem operation is completed and
MFC response is received.

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Executing a Complete
Instruction
Add (R3), R1
/* R1 [R1] + [[R3]]
Adds the contents of a memory location pointed to by R3
to register R1.

GENERAL STEPS:
1. fetch instruction
2. Fetch 1st operand (contents of memory location pointed by R3)
3. Perform addition
4. Load result into R1

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Executing a Complete Instruction

Sequence of control steps:

1. PCout, MARin, Read, Select4, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End
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Steps 1 3:
Instruction
fetch

 STEP 1: PCout, MARin, Read, Select4, Add, Zin

Instructn fetch by loading PC content into MAR & send
read request to mem. [PC] now onto bus
Select4->causes MUX to select const 4.
ALU->
Operand B-> [PC] from bus
Operand A -> Const value 4
Alu-> Now [PC]+4= [PC] -> Reg Z

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 STEP 2: Zout, PCin, Yin, WMFC

Reg Z-> back to PC while waiting for mem to respond

STEP 3: MDRout, IRin

Word fetched from mem loaded into IR
-----------------------------Fetch Instruction completed ----------------------------

STEP 4: R3out, MARin, Read

[R3]-> MAR and mem read operatn initiated

STEP 5: R1out, Yin, WMFC

[R1]-> Reg Y and wait till mem read opeatn of 1st operand is
completed

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STEP 6: MDRout, SelectY, Add, Zin

When MFC=1 (Read operatn completed) -> mem operand into MDR
[MDR] -> gated to the bus and Xferred to I/P B of ALU
ALU->
SelectY -> Reg Y (Contents of R1) -> Operand A
Operand B -> data from Bus<- MDR <- Mem locatn <- addr in R3
ADD
Result in Z

STEP 7: Zout, R1in, End

Z-> R1

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BRANCH INSTRUCTION (Pg 423)

for UNCONDITIONAL
1. PCout, MARIN, Read, Select4, ADD, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout , IRin
4. Offset-field-of-IRout, Add, Zin
5. Zout, PCin, End

FOR CONDITIONAL
4. Offset-field-of-IRout, Add, Zin, If N=0 Then End.
Fetch Cycle ends when instructn loaded into IR
Offset value is extracted from IR by instruction decoding ckt and
gated onto the bus
PC updated value -> in Reg Y -> ALU operand B
Offset -> Bus -> ALU operand A
ADD and O/P into Z -> addr where to branch next
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Multiple-Bus Organization
Single-bus structure: Control sequences are long as only one data
item can be transferred over the bus in a clock cycle.

Figure on next slide shows a three-bus structure.

All registers are combined into a single block called register file with
three ports: 2 outputs allowing 2 registers to be accessed
simultaneously and have their contents put on buses A and B, and 1
input allowing data on bus C to be loaded into a third register.

Buses A and B are used to transfer source operands to the A and B

inputs of ALU, and result transferred to destination over bus C.

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Multiple-Bus Organization (2)

Bus A Bus B

Bus C

Bus A Bus B

Bus C

Incrementer
Instruction
decoder

PC

IR

Register
file

MUX

Constant 4

MDR
A

ALU
R

MAR

Address
line
Memory bus
data lines
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Multiple-Bus Organization (3)

For the ALU, R=A (or R=B) means that its A (or B)

input is passed unmodified to bus C.

Add R4, R5, R6 /* R6 [R4] + [R5]
Adds the contents of R4 and R5 to R6.
Sequence of control steps:
1. PCout, R=B, MARin, Read, IncPC
2. WMFC
3. MDRoutB, R=B, IRin
4. R4outA, R5outB, SelectA, Add, R6in, End

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STEP 1:
Contents of PC are passed through ALU and stored into MAR to start mem
read operatn. At same time, PC incremented by 4.
Now [MAR] -> original PC value
[PC] -> updated PC value

STEP 2:

Processor waits for MFC and loads data received into MDR.

STEP 3:

MDR data transfered into IR through ALU using instructn R=B.

STEP 4:
Execution phase of instructn requires only 1 control step.

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Control
Generating of control signals are of 2 categories:
Hardwired control
Microprogrammed control.
Hardwired control:
Clock

CLK

Control step
counter

...

IR

:
:

External
inputs

Condition
codes

Decoder/
encoder

...
Control signals
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Memory bus
data lines

 Required control signals are determined

by following information:
1.
2.
3.
4.

Contents of control step counter

Contents of instruction register
Contents of CCR
External i/p signals such as MFC and interrupt requests

Here encoder/decoder ckt generates required control O/Ps

Depending on state of all its i/ps.

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Separation of decoding &

encoding functions(Fig7.11)

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 Step decoder provides a separate signal line for each

step or time slot, in the control sequence.
O/p of instructn decoder consists of a separate line for
each m/c instructn.
For any instructn loader in IR, one of the o/p lines INS 1
through INSm is set to 1 while rest to 0.
Encoder block I/P generates signals like Yin, PCout, Add,
End, etc.

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Eg: Zin= T1 +T6.ADD+T4.BR+..

This signal Zin is asserted during time slot T1 for all
instructions, during T6 for an ADD instruction, during T4
for an unconditional branch instruction and so on.

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The ckt that generates the End Control signal from the logic function,

End = T7 ADD + T5 BR + (T5 N + T4 N) BRN +

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Hardwired Control

The sequence of operation carried out by this m/c is determined by

wiring the logic elements, hence the name hardwired.
Hardwired control provides highest speed.
RISCs are implemented with hardwired control.
If the instruction set becomes very complex (CISCs) implementing
hardwired control is very difficult. In this case microprogrammed
control units are used.
In order to allow execution of register-to-register operations in a
single clock cycle, RISCs (and other modern processors) use threebus CPU structures

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 There are 4 techniques for design of

hardwired control unit.
1.State-table method:

It is a classical method of sequential ckt design.

It attempts to minimize the amount of h/w.

2.Delay-Element Method

It is heuristic method based on the use of clocked delay element( D FF) for
control signal timings.

3. Sequence- Counter Method

It uses counter for timing purposes.

4. PLA Method

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It uses a Programmable Logic Array(PLA)

State-table method

Here start with construction of state table

transition table.
In every state the control unit generates a
set of controls.Control unit trasmits from
one state to another state depending on
its:
1) current state
2) I/P to the controller

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State-table method

Eg: Hardwired control unit for multiplication of 2 unsigned numbers.

Flowchart is in the next slide.
Multiplicand=M, Multiplier=Q.
Register C handles carry if any during addition.
Initially Reg. C & Ac are cleared.
Seq. count reg. count set to n=No. of bits in the multiplier.
Next is a loop, that keeps forming the Partial products.
If Q=1,
M is added to AC.
Any carry from addition is transferred to C

Else no need of this action

The counter is decremented by 1.
Reg. C, AC, Q are then shifted once to the right to obtain the Partial
Product.

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State-table method:

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Delay-Element Method
The control signals from the control unit are
activated in a proper seq.
There is specific time delay b/w activation
of 2 groups of consecutive control signals.
A seq. of delay elements can be used to
generate control signals one after the other.
To ensure synchronous operation, the delay
elements are implemented by D FFs
controlled by a common clock signal.
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Delay-Element Method
A control unit using delay elements can be constructed
directly fro the flowchart that specifies required control
signal seq.
Every state requires a delay element.
The signals that activate same control signals are Ored
to get one common o/p signals.
When n lines in the flowchart merge to a common point,
then these lines are an n I/P OR gate.
A decision box can be implemented by 2 I/P AND gate.
The 1st I/P of each AND gate is driven by I/P A and
complement of A respectively.
While 2nd I/P of both gates is common and it is the O/P
of the delay element.
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Delay-Element Method

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A Complete Processor (Pg 428)

Instruction
unit

Integer
unit

Instruction
cache

Floatingpoint
unit

Data
cache

Businterface

Processor

Systembus
Main
memory

Figure7.14.

Input/
Output

Blockdiagramofacompleteprocessor.

 Instructn Unit->Fetches instructn from instructn cache or

main mem whn desired instructn is not already in cache.
Has separate processing units to deal with integer and
floating point data.
Data cache is inserted between these units and main
mem.
Today many processors use separate caches for
instructn and data
Processor connected to system bus and rest of
computer by means of bus interface.
A processor may include several integer and floating
point units to increase potential of concurrent
operations.
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 Microprogrammed control
Control signals generated by a program.
Control word (CW) is a microinstruction that contains individual bits
that represent the various control signals.

Vertical organization: highly encoded schemes that use compact

codes to specify only a small number of control functions in each
microinstruction.

Horizontal organization: minimally encoded scheme in which many

resources can be controlled with a single microinstructions.

Popular in Complex Instruction Set Architectures (CISC) because

complex instruction sets require complex controllers that can more
easily be implemented as microprograms.
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Memory bus
data lines

 A sequence of CWs corresponding to the control

sequence of M/C instruction constitutes MICROROUTINE
for that instruction.
Individual control words in this microroutine are called
MICROINSTRUCTIONS.
Microroutines for all instructions in instructn set of
computer are stored in a special mem called CONTROL
STORE.
To read control words sequentially from control store, a
MICROPROGRAM COUNTER(PC) is used.

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Control signals are generated by a program similar to machine language

programs.
Control Word (CW); microroutine; microinstruction

Example of a horizontal

R3out, MARin, Read

5.

R1out, Yin, WMFC

6.

MDRout, SelectY, Add, Zin

7.

Zout, R1in, End

WMFC
End

4.

R1 in
R3 out

MDRout, IRin

Z out
R1 out

3.

Z in

0
0
1
0
0
0
0

Zout, PCin, Yin, WMFC

Add

0
0
1
0
0
1
0

1
0
0
1
0
0
0

2.

Select

1
0
0
1
0
0
0

PCout, MARin, Read, Select4, Add, Zin

Y in

1
0
0
0
0
0
0

MDR out
IR jn

0
1
0
0
0
0
0

MAR in
Read

PC out

1
2
3
4
5
6
7

..

PC in

Microinstruction

organization scheme:

1.

0
1
0
0
1
0
0

1
0
0
0
0
0
0

1
0
0
0
0
1
0

1
0
0
0
0
1
0

0
1
0
0
0
0
1

0
0
0
0
0
0
1

0
1
0
0
1
0
0

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Memory bus
data lines

0
0
0
0
1
0
0

0
0
0
1
0
0
0

0
0
0
0
0
0
1

..

Select=0: SelectY
Select=1: Select4

Fig7.16 Basic organization of

microprogrammed control unit

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 To read control words sequentially from control store, a

PC (Micro Program Counter) is used.
Every time a new instructn is loaded into IR, O/P of
starting addr generator is loaded into PC.
PC is then automatically incremented by clock, causing
successive micro instructns to be read from control
store.
Hence control signals are delivered to various parts of
processor in correct sequence.

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Modification required in basic

organization
In case of branching instructn-> control unit is required to
check status of conditional codes or external i/ps or
choose between alternative course of action.
In Hardwired control-> this situation is handled by
including an appropriate logic function in encoder
circuitry.
In Microprogrammed control->In addn to branch addr,
these microinstructions specify which external i/ps,
conditional codes or bits of instruction register should be
checked as condition for branching to take place.

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 Eg: Microroutine for instructn branch<0

0 PCout, MARin, Read, Select4, Add, Zin
1 Zout, Pcin, Yin, WMFC
2 MDRout, IRin
3 Branch to starting addr of appropriate microroutine
---------------------------------25 If N=0, then branch to microinstructn 0
26 Offset-field-of-IRout, selectY, Add, Zin
27 Zout, PCin, End

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STEPS

After loading Instructn into IR, a Branch Microinstruction xfers

control to corresponding microroutine, which is assumed to start at
locatn 25 in control store.
This addr(25) is o/p of starting addr generator.
This Microinstruction at 25 tests Nbit of conditn codes.
If N=0 -> Branch to locatn 0 to fetch new m/c instructn
Else -> Microinstruction at locatn 26 is executed to put branch
target addr into reg Z.
Microinstruction in locatn 27 loads this addr into PC

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Figure7.18. Organizationofthecontrolunittoallowconditionalbranchingin
themicroprogram.
External
inputs
IR

Clock

Startingand
branchaddress
generator

Condition
codes

PC

Control
store

CW

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Microinstructions (Pg 433)

FORMAT OF INDIVIDUAL MICROINSRUCTIONS
A straightforward way to structure microinstructions is to
assign one bit position to each control signal.(See Fig in
next slide)
However, this is very inefficient as it results in long
microinstructions. Also only few bits are 1(active gating),
so available bit space is poorly used.
The length can be reduced: most signals are not needed
simultaneously, and many signals are mutually exclusive.
All mutually exclusive signals are placed in the same
group and are represented using binary coding scheme.
This reduces number of bits from 42 to 20 bits to store
pattern for 42 signals. So smaller control store.

Micro
instruction

PCout

MARin

Read

MDRout

IRin

Yin

Select

Add

Zin

Z out

R1out

R1 in

R3out

WMFC

End

Control signals are generated by a program similar to machine language

programs.
Control Word (CW); microroutine; microinstruction

PCin

Figure7.15 AnexampleofmicroinstructionsforFigure7.6.

Partial Format for the Microinstructions

Microinstruction
F1

F2

F3

F4

F5

F1(4bits)

F2(3bits)

F3(3bits)

F4(4bits)

F5(2bits)

0000:Notransfer
0001:PCout
0010:MDRout
0011:Zout
0100:R0out
0101:R1out
0110:R2out
0111:R3out
1010:TEMP
out
1011:Offsetout

000:Notransfer
001:PCin
010:IRin
011:Zin
100:R0in
101:R1in
110:R2in
111:R3in

000:Notransfer
001:MARin
010:MDRin
011:TEMPin
100:Yin

0000:Add
0001:Sub

00:Noaction
01:Read
10:Write

F6

F7

16ALU
functions

F8

F6(1bit)

F7(1bit)

F8(1bit)

0:SelectY
1:Select4

0:Noaction
1:WMFC

0:Continue
1:End

Figure7.19.

1111:XOR

What is the price paid for

this scheme?

Anexampleofapartialformatforfieldencodedmicroinstructions.

Eg: Here F4 contains only 4 bits that

specify one of the 16 ALU operations
Problem:
Grouping control signals into fields requires
alittel more hardware because decoding
ckts must be used to decode bit patterns.

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Further Improvement
Enumerate the patterns of required signals in all possible
microinstructions.
Each meaningful combination of active control signals
can then be assigned a distinct code that represents the
microinstruction.
Such full encoding further reduces microword lengths but
increases complexity of decoder ckts.
Vertical organization
Horizontal organization

 Vertical organization: highly encoded schemes that use

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compact codes to specify only a small number of control

functions in each microinstruction.
Horizontal organization: minimally encoded scheme in which
many resources can be controlled with a single
microinstructions
Horizontal organization is used when higher operating speed is
desired and when m/c structure allows parallel use of
resources.
Vertical results in slower operating speeds becoz more
microinstructions are needed to perform desired control
functions.

Microprogram Sequencing
If all microprograms require only straightforward
sequential execution of microinstructions except for
branches, letting a PC governs the sequencing
would be efficient.
However, two disadvantages:
Having a separate micro-routine for each machine instruction results
in a large total number of microinstructions and a large control store.
Longer execution time because it takes more time to carry out the
required branches.

Eg: Add src, Rdst (Adds source operand with Rdst reg contents)
Assume source operands can be specified in Four addressing
modes: register, autoincrement, autodecrement, and indexed (with
indirect forms of all 4).

 Flowchart of a microprogram for given

instruction(next slide)
Each box corresponds to a microinstruction that controls
Xfers and operations indicated in box.
Microinstruction IDs located at addr indicated by octal
no.

Branch addr modification using Bit-Oring

Fig shows that branches not always made to a single
branch addr becoz simple microroutines are combined to
share common parts.
At point , necessary to choose betwn actions required
by direct & indirect addressing modes.
If Indirect: then microinstruction at loactn 170 is
performed else 171 by bypassing 170.
Most efficient way to bypass 170 is to have the
preceding branch microinstructn specify addr 170 and
then use OR gate to change LSB of this addr to 1 if
direct addressing mode is involved.
Called bit-ORing technique

WIDE BRANCH ADDRESSING

Fig 7.20 included wide branch at locatn 003.

Instructn decoder generates addr of microroutine that implements
instructn loaded into IR.
Here IR contains ADD instructn for which decoder generates addr
101. But this 101 cannot be directly loaded into uPC.
5 possible addr modes as shown on diff branches at addr values
161, 141, 121, 101 and 111.
Bit-ORing technique is then used to modify starting addr generated
by decoder to reach appropriate path.

06/21/15

Mode
ContentsofIR

OPcode

11 10

Rsrc
8 7

Rdst
4 3

Address
(octal)

Microinstruction

000

PCout,MARin ,Read,Select4 ,Add,Zin

001

Zout,PCin,Yin,WMFC

002

MDRout,IRin

003

Branch{ PC 101(fromInstructiondecoder);

PC5,4 [IR10,9]; PC3 [IR10] [IR9] [IR8]}

Note:

121

Rsrcout,MARin ,Read,Select4,Add,Z
in

122

Zout,Rsrcin

123

Branch{ PC 170;PC0 [IR8]},WMFC

170

MDRout,MARin,Read,WMFC

171

MDRout,Yin

172

Rdstout ,SelectY,Add,Zin

173

Zout,Rdstin,End

Figure7.21. MicroinstructionforAdd(Rsrc)+Rdst.
Microinstructionatlocation170isnotexecutedforthisaddressingmode.

Microinstructions with NextAddress Field

The microprogram we discussed requires several branch
microinstructions, which perform no useful operation in
the datapath but are used only to determine addr of next
instructn.
A powerful alternative approach is to include an address
field as a part of every microinstruction to indicate the
location of the next microinstruction to be fetched.
Pros: separate branch microinstructions are virtually
eliminated; few limitations in assigning addresses to
microinstructions.
Cons: additional bits for the address field (around 1/6
capacity of control store would be devoted to
addressing)

Here each instructn contains addr of next instructn, so no need to PC

and hence is replaced with AR (microinstructn addr register)

This AR is loaded from next-addr field in each microinstructn.

Next addr bits are fed through OR gates to AR.

06/21/15

Microinstructions with NextAddress Field

IR

External
Inputs

Condition
codes

Decodingcircuits

AR

Controlstore

I R

Nextaddress

Microinstructiondecoder

Controlsignals

Figure7.22.Microinstructionsequencingorganization.

Microinstruction
F0

F1

F0(8bits)

F1(3bits)

Addressofnext
000:Notransfer
microinstruction 001:PCo ut
010:MDRo ut
011:Zo ut
100:Rsrcout
101:Rdstout
110:TEMPou t

F4

F5

F2

F3

F2(3bits)

F3(3bits)

000:Notransfer
001:PCin
010:IRin
011:Zin
100:Rsrcin
101:Rdstin

000:Notransfer
001:MARin
010:MDRin
011:TEMPin
100:Yin

F6

F7

F4(4bits)

F5(2bits)

F6(1bit)

F7(1bit)

0000:Add
0001:Sub

00:Noaction
01:Read
10:Write

0:SelectY
1:Select4

0:Noaction
1:WMFC

F9

F10

1111:XOR

F8

F8(1bit)

F9(1bit)

F10(1bit)

0:NextAdrs
1:InstDec

0:Noaction
1:ORmo de

0:Noaction
1:ORind src

Figure7.23.

FormatformicroinstructionsintheexampleofSection7.5.3.

Implementation of the
Microroutine
Octal
address
0
0
0
0

0
0
0
0

0
0
0
0

1 2 1
1 2 2

0 1 0 1 0 0 1 0 1 0 0 01 1 0 0 1 0 0 0 0 01
0 1 1 1 1 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 00

1
0

0
1

0
0

0
0

0
1

1
1
1
1

0
0
0
0

0
0
0
0

1
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
1
1
0

0
1
1
0

1
0
1
0

1
0
1
0

0
0
0
0

0
0
1
0

0
1
1
0

1
1
0
1

1
1
0
0

0
0
1
1

01
00
01
00

00
00
01
10

1
1
0
0

0
0
1
1

0
1
0
0

0
1
0
0

0
0
0
0

0
0
0
0

1
0
0
0

1
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

F6 F7 F8 F9 F10
0
0
0
0

1
1
1
0

0
0
0
0

F5

0
0
0
1

1
1
1
0

0
0
0
0

F4

0
0
0
1

1
1
1
0

0
0
0
0

F3

0
1
0
0

1
1
1
0

0
0
0
0

F2

1
0
0
0

0
1
2
3

0
0
0
0

F1

1
0
0
0

7
7
7
7

0
1
2
3

F0

0
0
0
0

1
0
0
0

Figure7.24.ImplementationofthemicroroutineofFigure7.21usinga
nextmicroinstructionaddressfield. (SeeFigure7.23forencodedsignals.)

Prefetching
Drawback of microprogrammed control:
Leads to slower operating speed becoz of the time it takes
to fetch microinstructions from control store.
Faster operation is achieved if next instruction is prefetched
while current one is being operated.
Thus execution time can be overlapped with fetch time.
Some difficulties:
Status flags and result of currently executed microinstructns
are needed to determine addr of next microinstructn.
Thus straightforward prefetching occasionally prefetches a
wrong microinstructn.In such cases, fetch must be repeated
with correct addr.

EMULATION
If we add to the instructn set of Computer M1, an entire new
set of instructions which belong to computer M2,Programs
written in m/c language of M2 can then be run on computer
M1 i.e M1 emulates M2.
Emulation allows to replace obsolete equipment with more upto-date machines.
If replacement computer fully emulates original one, then no
s/w changes is to be made to run existing programs.
Thus emulation facilitates transitions to new computer
systems with minimal disruption.
Emulation easy with computers having same architectures but
can succeed with those having totally different architectures.

06/21/15

EMULATION

Emulation is best described as imitating a certain computer platform

or program on another platform or program. In this manner, it is
possible to view documents or run programs on a computer not
designed to do so.
An emulator is itself a program that creates an extra layer
between an existing computer platform (host platform) and the
platform to be reproduced (target platform).

06/21/15

COMPARE SIMULATOR&
EMULATOR
A simulator is a software that duplicates some processor
in almost all the possible ways.
An emulator is a hardware which duplicates the features
and functions of a real system, so that it can behave like
the actual system. Difference between model and real
system operation called-> credibility gap