CHAPTER 3 THE DEVICE

Prepared by Azhani binti Hashim

A First Glance at the Diode

simplest of the semiconductor devices.
two homogeneous regions of p and n type
material separate by a thin region called
step or abrupt junction.
The p-type material is doped with acceptor
impurities (boron), which results in the
presence of holes as the dominant or
majority carriers.
The n-type material is doped with donor
impurities (phosphorus or arsenic), which
results in the presence of electron as the
dominant or majority carriers.
Aluminum contacts provide access to the

A First Glance at the Diode

Aluminum contacts provide access to
the p-terminal and n-terminals of the
device.

The Depletion Region Of

Diode
Bringing the p- and n-type
materials together causes a
large concentration gradient
at the boundary. This
gradient causes electrons to
diffuse from n to p and holes
to diffuse from p to n.
When the holes leave the ptype material, they leave
behind immobile acceptor
ions, which are negatively
charged.
Similarly, a positive charge
builds up on the n-side of
the boundary as the

The Depletion Region

The region at the junction, where the
majority carriers have been removed
leaving the fixed acceptor and donor
ions, is called the depletion or spacecharge region.
The charges create an electric field
across the boundary, directed from the
n to the p-region. It causes electrons to
drift from p to n and holes to drift from
n to p.

Design Abstraction Level

The MOS(FET) Transistor

The metal-oxide-semiconductor fieldeffect transistor (MOSFET or MOS, for
short) is certainly the workhorse of
contemporary digital design.
Its major asset from a digital
perspective is that the device performs
very well as a switch, and introduces
little parasitic effects.
Other important advantages are its
integration density combined with a
relatively simple manufacturing
process, which make it possible to

The MOS(FET) Transistor

The MOSFET is a four terminal device.
Circuit symbols for the various MOS
transistors are shown with four-port device
with gate, source, drain, and body terminals.
The voltage applied to the gate terminal
determines if and how much current flows
between the source and the drain ports.
The body represents the fourth terminal of the
transistor. Its function is secondary as it only
serves to modulate the device characteristics
and parameters.

The MOS(FET) Transistor

Two types of MOSFET devices.
The NMOS transistor consists of n+ drain and
source regions, embedded in a p-type
substrate. The current is carried by electrons
moving through an n-type channel between
source and drain. PMOS is the vice versa of
NMOS.
This is in contrast with the pn-junction diode,
where current is carried by both holes and
electrons.

The MOS(FET) Transistor

The transistor can be considered to be a
switch. When a voltage is applied to the gate
that is larger than a given value called the
threshold voltage, VT, a conducting channel is
formed between drain and source.
The larger the voltage difference between
gate and source, the smaller the resistance of
the conducting channel and the larger the
current.
When the gate voltage is lower than the
threshold, no such channel exists, and the
switch is considered open.

MOS Transistor under

Static Conditions
Cut-off Region
VGS = 0, drain, source and bulk are
connected to ground. Both junctions have a
0 V bias and considered off, which results in
an extremely high resistance between drain
and source.

Cut-off region

MOS Transistor under

Static Conditions
Linear / Resistive Region
Assume a positive voltage is applied to the gate.
The gate and substrate form the plates of a
capacitor with the gate oxide as the dielectric.
The positive gate voltage causes positive charge
to accumulate on the gate electrode and
negative charge on the substrate side.
Hence, a depletion region is formed below the
gate. This depletion region is similar to the one
occurring in a pn-junction diode.

linear region

MOS Transistor under

Static Conditions
Linear / Resistive Region (cont.)
As the gate voltage increases, the potential
at the silicon surface at some point reaches
a critical value, where the semiconductor
surface inverts to n-type material. This point
is the start of a phenomenon known as
strong inversion.

linear region

 The value of VGS where strong inversion

occurs is called the threshold voltage

MOS Transistor under

Static Conditions
Linear / Resistive Region (cont.)
Further increases in the gate voltage
produce no further changes in the depletion
layer width, but result in additional
electrons in the thin inversion layer directly
under the oxide.
Hence, a continuous n-type channel is
formed between the source and drain
regions, the conductivity of which is
modulated by the gate-source voltage.

MOS Transistor under

Static Conditions

- gamma is called the body-effect

coefficient.
Fermi Potential.
The threshold voltage, VT has a positive
value for a typical NMOS device, while it
is negative for a normal PMOS
transistor.

MOS Transistor under

Static Conditions
Linear / Resistive Region (cont.)
Assume now that VGS > VT and that a small
voltage, VDS, is applied between drain and
source. The voltage difference causes a
current ID to flow from drain to source.
VGS < VT
VDS < VGS VT

MOS Transistor under

Static Conditions
Therefore;

The operation region where Eq. (3.25) holds

is hence called the resistive or linear region.
One of its main properties is that it displays
a continuous conductive channel between
source and drain regions.

MOS Transistor under

Static Conditions
Saturation Region
As the value of the drain-source voltage, V DS
is further increased, the assumption that
the channel voltage is larger than the
threshold all along the channel ceases to
hold. At that point, the induced charge is
VGSzero,
< VT and the conducting channel disappears
or is pinched off.
VDS > VGS VT
Saturation region

MOS Transistor under

Static Conditions
The Saturation Region (cont.)
the channel thickness gradually is
reduced from source to drain until
pinch-off occurs. Under those
circumstances, the transistor is in the
saturation region, and Eq. (3.25) no
longer holds. The current remains
constant.

MOS Transistor under

Static Conditions
Channel-Length Modulation
The equation in 3.29 seems to suggest that
the transistor in the saturation mode acts as
a perfect current source. The current
between drain and source terminal is a
constant, independent of the applied
voltage, VDS over the terminals.
This not entirely correct. The effective
length of the conductive channel, L is
actually modulated by the applied VDS.
As can be observed from Eq. (3.29), the
current increases when the length factor L is
decreased. A more accurate description of
the current of the MOS transistor is

MOS Transistor under

Static Conditions
Channel-Length Modulation (cont)

an empirical parameter, called the

channel-length modulation.

MOS Transistor under

Static Conditions
Velocity Saturation
the velocity of the carriers is
proportional to the electrical field. In
other words, the carrier mobility is a
constant.

MOS Transistor under

Static Conditions
Velocity Saturation (cont)
However, at high field strengths, the
carriers fail to follow this linear model. In
fact, when the electrical field along the
channel reaches a critical value c, the
velocity of the carriers tends to saturate
due to scattering effects (collisions suffered
by the carriers).

MOS Transistor under

Static Conditions
Velocity Saturation (example)

For p-type silicon, the critical field at which

electron saturation occurs is around 1.5 x
106 V/m (or 1.5 V/m), and the saturation
velocity sat approximately equals 105 m/s.
This means that in an NMOS device with a
channel length of 1 m, only a couple of

I-V Plot for NMOS

Two NMOS transistors implemented in
the same technology and with the same
W/L ratio = 1.5.
The main difference however is that the
first device has a long channel length
(Ld = 10 m), while the second
transistor is a short channel device (Ld
= 0.25 m) and experiences velocity
saturation.

I-V Plot for NMOS

Long-channel device Quadratic

dependence.
Short-channel device Linear

I-V Plot for NMOS

CMOS Latch-Up
Latch up pertains to a failure
mechanism where a parasitic Silicon
Controlled Rectifier (SCR) is
inadvertently created within a circuit,
causing a high amount of current to
continuously flow through it once it is
accidentally triggered or turned on.
Depending on the circuits involved, the
amount of current flow produced by this
mechanism can be large enough to
result in permanent destruction of the
device due to Electrical OverStress
(EOS).

CMOS Latch-Up

The SCR (n-p-n-p structure) is formed by the

source of the NMOS, the p-substrate, the nwell and the source of the PMOS.

CMOS Latch-Up
Effect:
CMOS transistor not functioning
properly.
If the transistor gain and resistance
increase continuously, latch-up current
can permanently damage or destroying
junctions. Therefore, the transistor
cant be use.

CMOS Latch-Up
Prevention:
1. Latch up-resistant design where a layer of
insulating oxide (called a trench) surrounds
both the NMOS and the PMOS transistors.
This breaks the parasitic SCR structure
between these transistors.

CMOS Latch-Up
Prevention:
2. Reduce the well and substrate resistances
will producing lower voltage drops.
Higher substrate doping level.
Low resistance contact to GND.
Guard rings around p-well or n-well.