The 8051 MicroController

In this class, we will be discussing

the MCS-51 family of
microcontrollers, in particular the
8051 architecture, which is the
generic IC representative of this
family.

Important 8051 Features

4K bytes ROM
128 bytes RAM
Four 8-bit I/O ports
Two 16-bit timers
Serial interface
64K external code memory space
64K external data memory space

8051 Block Diagram

Pin Layout
The 8051 is a 40 pin device, but
out of these 40 pins, 32 are used
for I/O.
24 of these are dual purpose, i.e.
they can operate as I/O or a control
line or as part of address or date
bus.

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

8051
(8031)

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vcc
P0.0(AD0
)P0.1(AD1)
P0.2(AD2
P
) 0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14
)P2.5(A13
P
) 2.4(A12
)P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)

Pins of 8051 1/4

Vcc pin 40
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GND pin 20 ground
XTAL1 and XTAL2 pins 19,18
These 2 pins provide external clock.
Way 1 using a quartz crystal oscillator
Way 2 using a TTL oscillator
Example 4-1 shows the relationship between XTAL and the
machine cycle.

Pins of 8051 2/4

RST pin 9 reset
It is an input pin and is active high normally low .
The high pulse must be high at least 2 machine cycles.
It is a power-on reset.
Upon applying a high pulse to RST, the microcontroller will
reset and all values in registers will be lost.
Reset values of some 8051 registers
Way 1 Power-on reset circuit
Way 2 Power-on reset with debounce

Pins of 8051 3/4

EA pin 31 external access

There is no on-chip ROM in 8031 and 8032 .
The EA pin is connected to GND to indicate
the code is stored externally.
PSEN ALE are used for external ROM.
For 8051, /EA pin is connected to Vcc.
PSEN pin 29 program store enable
This is an output pin and is connected to the
OE pin of the ROM.
9

Pins of 8051 4/4

ALE pin 30 address latch enable
It is an output pin and is active high.
8051 port 0 provides both address and data.
The ALE pin is used for de-multiplexing the address and data by
connecting to the G pin of the 74LS373 latch.
I/O port pins
The four ports P0, P1, P2, and P3.
Each port uses 8 pins.
All I/O pins are bi-directional.

10

Reset Operation

To reset the 8051, the RST pin

must be held high for at least 2
machine cycles.
This can be achieved upon power
up using an RC network.
The 2 circuits for achieving this,
one is a manual reset, the other is
a power-on reset.
How does the 2 circuit works?
Try to remember capacitor is open
during steady-state.

Two circuits for system reset. (a) Manual reset (b) Power-on reset.

RESET Value of Some 8051 Registers:

Register
PC
ACC
B
PSW
SP
DPTR

Reset Value
0000
0000
0000
0000
0007
0000

RAM are all zero.

13

Oscillator ( clock) Input

The 8051 is typically driven by a
crystal oscillator connected to pin
18 and 19 as shown in fig
The words XTAL is short for crystal.

XTAL Connection to 8051

Using a quartz crystal oscillator

We can observe the frequency on the XTAL2 pin.
C2
XTAL2
30p
F
C1
XTAL1
30p
F
GND

15

XTAL Connection to an External Clock Source

XTAL2

N
C

Using a TTL oscillator

XTAL2 is unconnected.

EXTERNAL
OSCILLATOR
SIGNAL

XTAL1

GND

16

Machine Cycle and Clock

Cycle
12 clock cycles make one machine
cycle as shown in fig 2-5.
E.g. if we use a 12 MHz oscillator,
each clock cycle will have a time
period of 1/12MHz. Twelve of these
make one machine cycle so 12 x
(1/12 MHz) = 1 microsecond. Thats
the time of 1 machine cycle.

Relationship between oscillator clock cycles, states, and the machine cycle

Example :
Find the machine cycle for
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz;
machine cycle = 1 / 921.6 kHz = 1.085 s
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 s

19

Port 0 and Port 1

Port 0 is a dual purpose port, it is
located from pin 32 to pin 39 (8 pins)
and is labeled as AD0 to AD7.
Port 1 is a dedicated I/O port from pin
1 to pin 8. It is generally used for
interfacing to external device thus if
you need to connect to switches or
LEDs, you could make use of these 8
pins.

Port 2 and Port 3

Like port 0, port 2 is a dual-purpose port. It
can be used for general I/O or as the high
byte of the address bus for designs with
external code memory.
Port 3 is also dual purpose but designers
generally
avoid
using
this
port
unnecessarily for I/O because the pins
have alternate functions which are related
to special features of the 8051.
Indiscriminate use of these pins may
interfere with the normal operation of the
8051.

Alternate Pin-functions

A Pin of Port 0
Read latch

Internal
CPU bus
Write to
latch

TB2

P0.X
pin

D
QP1.X
M1
Clk
Q
TB1

Read pin

8051 IC
7/4/15

23

Hardware Structure of I/O Pin

Each pin of I/O ports
Internal CPU bus communicate with CPU
A D latch store the value of this pin
D latch is controlled by Write to latch
Write to latch 1 write data into the D latch
2 Tri-state buffer
TB1: controlled by Read pin
Read pin 1 really read the data present at the pin
TB2: controlled by Read latch
Read latch 1 read value from internal latch
A transistor M1 gate
Gate=0: open
Gate=1: close
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24

Tri-state Buffer
Output

Input

Tri-state control
(active high)

7/4/15

Low

Highimpedance
(open-circuit)

25

Port 0 pins 32-39

P0 is an open drain.
Open drain is a term used for MOS chips in the same way
that open collector is used for TTL chips.
When P0 is used for simple data I/O we must connect it to
external pull-up resistors.
Each pin of P0 must be connected externally to a 10K ohm
pull-up resistor.
With external pull-up resistors connected upon reset, port 0
is configured as an output port.

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26

Port 0 with Pull-Up Resistors

Vcc

7/4/15

Port 0

P0.0
DS500 P0.1
P0.2
0
P0.3
8751 P0.4
P0.5
8951 P0.6
P0.7

10
K

27

Dual Role of Port 0

When connecting an 8051/8031 to an external memory, the 8051
uses ports to send addresses and read instructions.
8031 is capable of accessing 64K bytes of external memory.
16-bit address P0 provides both address A0-A7, P2 provides
address A8-A15.
Also, P0 provides data lines D0-D7.
When P0 is used for address/data multiplexing, it is connected to the
74LS373 to latch the address.
There is no need for external pull-up resistors as shown in
Chapter 14.

7/4/15

28

74LS373
PSEN
ALE
P0.0
P0.7

G
D

74LS3
73

OE
O
C
A0
A7
D0
D7

EA
P2.0
P2.7

7/4/15

8051

A8
A15

ROM

29

Reading ROM (1/2)

PSEN
ALE
P0.0
P0.7

2. 74373
latches the
address and
74LS3
send
to ROM

1. Send address
to ROM
G
D

73

OE
O
C
A0
A7

Address
D0
D7

EA
P2.0
P2.7

8051
7/4/15

A8
A12

ROM
30

Reading ROM (2/2)

PSEN
ALE
P0.0
P0.7

2. 74373
latches the
address and
send to ROM

74LS3
73

D
Address

OE
O
C
A0
A7
D0
D7

EA

3. ROM send the

instruction back
P2.0
P2.7

7/4/15

8051

A8
A12

ROM

31

ALE Pin
The ALE pin is used for de-multiplexing the
address and data by connecting to the G pin of
the 74LS373 latch.
When ALE=0, P0 provides data D0-D7.
When ALE=1, P0 provides address A0-A7.
The reason is to allow P0 to multiplex address and
data.

7/4/15

32

Port 2 pins 21-28

Port 2 does not need any pull-up resistors
since it already has pull-up resistors internally.
In an 8031-based system, P2 are used to
provide address A8-A15.

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33

Port 3 pins 10-17

Port 3 does not need any pull-up resistors since it already
has pull-up resistors internally.
Although port 3 is configured as an output port upon reset,
this is not the way it is most commonly used.
Port 3 has the additional function of providing signals.
Serial communications signal RxD, TxD
External interrupt /INT0, /INT1
Timer/counter T0, T1
External memory accesses in 8031-based
system /WR, /RD

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Port 3 Alternate Functions

7/4/15

P3 Bit

Functio
n

Pin

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RxD
TxD
INT0
INT1
T0
T1
WR
RD

10
11
12
13
14
15
16
17
35

A Pin of Port 1
Read latch

Internal
CPU bus
Write to
latch

TB2

Vcc
Load(L1
)

D
QP1.X

P1.X
pin

M1
Clk
Q
TB1

Read pin

8051 IC
7/4/15

36

Writing 1 to Output Pin P1.X

Read latch

Vcc

TB2

1. write a 1 to the
pin
Internal
CPU bus
Write to
latch

D
QP1.X

1
0

Load(L1
)
M1

2. output
pin is Vcc
P1.X
pin

output 1

Clk
Q
TB1

Read pin

8051 IC
7/4/15

37

Writing 0 to Output Pin P1.X

Read latch

Vcc

TB2

1. write a 0 to the
pin
Internal
CPU bus
Write to
latch

D
QP1.X

Load(L1
)

2. output
pin is
ground
P1.X
pin

M1

output 0

Clk
Q
TB1

Read pin

8051 IC
7/4/15

38

Reading High at Input Pin

Read latch
TB2

1. write a 1 to the pin MOV

P1,#0FFH
Internal CPU
bus

2. MOV A,P1

Vcc
Load(L1)

D
QP1.X

Write to latch

external
pin=High
P1.X pin

M1

Clk
Q
TB1
Read pin
3. Read pin=1 Read
latch=0 Write to
latch=1
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8051 IC
39

Reading Low at Input Pin

Read latch

Vcc

2. MOV A,P1

TB2

1. write a 1 to the pin

Load(L1)

external pin=Low

MOV P1,#0FFH
Internal CPU
bus

D
QP1.X

Write to latch

P1.X pin

M1

Clk
Q
TB1
Read pin
3. Read pin=1 Read
latch=0 Write to
latch=1
7/4/15

8051 IC
40

Memory Structure
While most microprocessors implement a
shared memory space for data and code
(programs), microcontrollers has limited
memory and the program is usually stored
in ROM.
In the 8051, both code and data may be
internal but they are stored in separate
memories, namely the internal ROM and
RAM. Expandable to a max of 64K using
external memory.
The next page shows the 8031 which has
no internal ROM.

Summary of the 8031 memory spaces

Summary of the 8051 on chip data memory

Register Banks
4 Register Banks Bank0, Bank1,
Bank2 and Bank3
Each Bank consists of R0, R1,
R2, R3, R4, R5, R6, R7
Bank 0 is the default upon power
up of the microcontroller
Other banks can be selected by
programming PSW register.

 RAM memory space allocation in the 8051

7FH
Scratch pad RAM
30H
2FH
Bit-Addressable RAM
20H
1FH
18H
17H
10H
0FH
08H
07H
00H

Register Bank 3
Register Bank 2
Register Bank 1) Stack(
Register Bank 0

45

General Purpose RAM

The general purpose RAM area is
from address 30H to 7FH. The
locations from address 20H to 2FH
can also be used as general
purpose RAM although these
addresses have very specific role.

Bit-Addressable RAM
The 8051 contains 210 bitaddressable locations of which 128
are at byte address 20H through
2FH.
This is the powerful feature of
most
microcontroller
because
individual bits can be set, cleared,
ANDed, ORed etc. with a single
instruction instead of having to

8051 Flag bits and the PSW

register
PSW Register
CY

AC

F0

RS1

RS0

OV

--

Carry flag PSW.7CY

Auxiliary carry flag PSW.6AC
Available to the user for general purpose
PSW.5-Register Bank selector bit 1 PSW.4RS1
Register Bank selector bit 0 PSW.3RS0
Overflow flag PSW.2OV
User define bit
PSW.1-Parity flag Set/Reset odd/even parity
PSW.0P

RS1 RS0

Register Bank

Address

00H-07H

08H-0FH

10H-17H

18H-1FH

1
1

0
1

48

Stack in the 8051

The register used to access
the stack is called SP (stack
pointer) register.

7FH
Scratch pad RAM
30H

The stack pointer in the

8051 is only 8 bits wide,
which means that it can take
value 00 to FFH. When
8051 powered up, the SP
register contains value 07.

2FH
Bit-Addressable RAM
20H
1FH
18H
17H
10H
0FH
08H
07H
00H

Register Bank 3
Register Bank 2
Register Bank( Stack)
1
Register Bank 0

49

Special Function Registers

Above 7FH, there is another block
of memory 80H to 0FFH in all the
version of MCS51 uP
this 128 bytes of memory are
reserved for Special Function
Register (SFR). There are 21 SFRs.

SFRs
SFR are usually addressed by name
Memory location 0F0H is given a name
called Register B, similarly 80H is called
P0.
Not all memory location has a name
memory location 35H has no name

Some locations between the SFRs have

no names as well e.g. 91H.
Such
locations should not be used to store
any data. If you do it then your data
may be lost.
Some important or commonly used
SFRs will be discussed while others will
be explained when you need to use
them in your projects.

Special Function Registers

Name

Function

Internal RAM
address (hex)

PCON

Power control

87

PSW

Program status word 0D0

SCON

Serial port control

98

SBUF

Serial port data

buffer

99

SP

Stack pointer

81

TMOD

timer./counter mode 89

TCON

Timer control

88

TL0

Timer 0 low byte

8A

TH0

Timer 0 high byte

8C

TL1

Timer 1 low byte

8B

TH1

Timer 1 high byte

8D

Special Function Registers

Commonly used SFRs

Accumulator, it has two names, A

and ACC. Many instruction make
use of the accumulator, eg: mov
A,R0, push acc
SP, always pointing to the top of
the stack, increasing by 1 before
write to stack, decreasing by 1
after read from stack

Program Status Word (PSW)

This is a very important register
because it contains status bits which
indicates the current state of the cpu.
PSW.7 CarrY (CY)
PSW.6 Aux Carry (AC)
PSW.5 Flag 0 (F0)
PSW.4 Register Bank Select 1
PSW.3 Register Bank Select 0
PSW.2 Overflow(OV)
PSW.1 reserved
PSW.0 Even Parity Flag (P)

Accessing External Code Memory

If the design involves external
code memory, both P0 and P2
should not be used as general
purpose I/O since P2 is now the
Higher address bus while P0 is the
multiplexed Lower address bus and
the data bus.
As stated earlier, the PSEN pin
must be used.

74LS373
PSEN
ALE
P0.0
P0.7

G
D

74LS3
73

OE
O
C
A0
A7
D0
D7

EA
P2.0
P2.7

7/4/15

8051

A8
A15

ROM

57

Reading ROM (1/2)

PSEN
ALE
P0.0
P0.7

2. 74373
latches the
address and
74LS3
send
to ROM

1. Send address
to ROM
G
D

73

OE
O
C
A0
A7

Address
D0
D7

EA
P2.0
P2.7

8051
7/4/15

A8
A12

ROM
58

Reading ROM (2/2)

PSEN
ALE
P0.0
P0.7

2. 74373
latches the
address and
send to ROM

74LS3
73

D
Address

OE
O
C
A0
A7
D0
D7

EA

3. ROM send the

instruction back
P2.0
P2.7

7/4/15

8051

A8
A12

ROM

59

Multiplexing the address bus (low-byte) and data bus

Accessing external code memory

FIGURE 211

Timing for MOVX instruction

Internal Timers
Original 8051 has 2 timers
16 bits

16 bits

TH0 : TL0

TH1 : TL1

Timer 0

Timer 1

Timers increment on each system clock

Timer registers (TH0, TL0, TH1, TL1) can be read or written to
Timer overflow can cause interrupts or set SFR bits high

Timer/Counter Logic

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PROGRAMMING 8051 TIMERS

Timer 0 registers
TL0 ( timer 0 low byte )
TH0 ( timer 0 high byte )

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Timer 1 registers
TL1 ( timer 1 low byte )
TH1 ( timer 1 high byte )

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TMOD (timer mode) register

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7/4/15

68

Operation of Timer on
Mode-0

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Operation of Timer in
Mode 1

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Operation of Timer in
Mode 2

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Operation of Timer in
Mode 3

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