ECE238L FALL 2015

LAB 0
DESIGN AND SIMULATE GATES
Fundamentals of Digital and Computer Design with VHDL
Experiment 0A & 0B
Anees Abrol (aabrol@unm.com)
Eric Hamke (ehamke@unm.com)
Steven Seppala (sseppala@unm.edu)
Amir Raeisi Nafchi (amirorn@unm.edu)
Bhuwan Babu Bastola (bhuwanbabu@unm.edu)

LEARNING OBJECTIVES

Implement logic gates.

Implement logic designs based on
DeMorgans Law.
Simulate your design to verify it works
Introduction to ISE, Adept, and basic
VHDL

VHDL CODE INTRO

VHDL designs have three parts: library, entity

declaration, architecture declaration.
Entity and Architecture are the textual descriptions
of the circuit
Signal assignment symbol <=
End code with ;
Identifiers: Signal names (I/O ports) and labels
(entity and architecture names).
Not case sensitive. No convention for spaces and
indentation.
Label used in entity declaration must be used in
architecture.
Precedence: NOT, AND, OR

SAVING YOUR LAB WORK

You all should have an ECE login and password
for this class. If not see Frank Mercer. He will set
you up.
Get an access card for after hours access to ECE.
Create a working directory on your
computer or a Flashdrive (Flashdrive is
better)
Temp/Your_Name/ECE238L/Lab#
No spaces
Alphanumeric with underscore only!!

These two steps are very important. You must know

where you are saving your work on your computer!

START A NEW PROJECT

Enter
AND_3
Enter
working directory
on your
computer or
Flashdrive
(Flashdrive is
better)

When done entering data

Click on Next>

SELECT BOARD AND LANGUAGE

TYPE

ALWAYS Check
These
- Spartan 6
- XC6SLX16
- CSG324
- VHDL
Debugging Tip:
The fields marked in
yellow are not
always populated
with data specific to
the boards in the
lab.

If these are not

correct you will have
When done checking data errors when you
Click on Next>
attempt to generate

COMPLETE THE PROJECT SETUP

and_3

Check that these

are setup
correctly

Project Name you

Entered
Working
directory on your
computer or
Flashdrive
(Flashdrive is
better)

If things do not look right

When done checking data
Click on <Back and re-enter data
Click on Finish

ADD NEW SOURCE

1. Right-click in
the Design Panel
(Upper left hand
side of screen.)
2. Choose New
Source from
pop-up menu

3. Select
VHDL module

4. Enter
AND_3

5. Check path
is correct.

When done entering data

Click on Next>

ENTER SOURCE INFORMATION

1. Enter the entity name

2. Enter the
architecture name
3. Enter the input
names
4. Enter the output
name
5. Update Direction
to out for output

When done entering data Click on

Next>

ADD VHDL CODE FOR 3-BIT AND

GATE

Debugging tip:
The assignment
VHDL deals with data
flows so you need to
be aware that
F<=A
Is not the same as
A <=F

Enter the logic function between the

begin and end Boolean_Function
statements

The first statement

says move values in A
into F, where the
second statement
moves values from F
into A

SYNTHESIZE TO CHECK CODE

Left click on the
symbol next to
Synthesize
to run a syntax check
If the syntax is correct you will get the following
message in the bottom console panel,

If something failed the check, a message indicating the line number and
a hint as to what failed.
Debugging Tip: Always fix the first item on the list first. Some of the
other messages may have been a result of the first lines error,

CREATE TEST BENCH

1. Right-click in
the Design Panel
(Upper left hand
side of screen.)
2. Choose New
Source from
pop-up menu

4. Enter
AND_3_TB
3. Select
VHDL Test
Bench

When done
entering data
Click on Next>

Debugging Tip: Do not name the test bench file exactly the same name
as the module. You will over write the module and have to reenter it.

ASSOCIATE SOURCE FOR TEST

BENCH
1. Select the
module that
the test bench
is for.

When done selecting the file Click

on Next>

TEST BENCH SUMMARY

Working directory on your

computer or Flashdrive
(Flashdrive
is better)
Check that these
are setup
correctly
Test Bench Name you Entered
VHDL Design being tested

When done
checking data
Click on Finish

COMBINATORIAL LOGIC HAS NO

CLOCKS
1. Comment out the clock period line (line 58) in
the Test Bench File using double dash as shown
below
2. Highlight lines 71 to
77 and right click

3. Choose
Comment
from pop-up
menu

4. Choose
Lines from
pop-up
menu

CREATE THE STIMULUS

The test bench file is an automated
test of your design. The software
will simulate what happens when
each line in the truth table is
applied to the inputs. So you need
to have worked out the truth table
in advance.

Replace the text

indicated above
with the following
representation of
the truth table.
Note the wait times at the end of each line,
this is how long the stimulus is active on the
input pins of the FPGA chip.

RUN SIMULATION
1. Select the simulation mode
radio button in the upper left hand
panel
2. Select test bench file to be
used by the simulation.

3. Expand the ISM

Simulation dropdown
menu
4. Select simulate
behavioral model

VIEWING SIMULATION RESULTS

se the

icon to expand the view so that you can see the wave forms.

WAVEFORM AFTER EXPANDING VIEW

Test sequence
A low (0);
B high (1);
C low (0);
Function output (F) is Low

his is one way of checking whether the design works or not.

ebugging Tip: This is a good tool for spotting timing errors.

Please Close Simulation Window

VIEW SCHEMATIC OF BLACK BOX

1. Select the implementation mode
radio button in the upper left hand
panel

3. Select start with a schematic

view.

2. Expand Synthesize drop down

menu

4. Click OK to
continue

AND_3 BLACK BOX

. Double click on the black box drawing to see the next layer (Look Up Table) dra

2. Double click on
the lut drawing to
see the design
summary windows

AND_3 DIALOG WINDOWS

Window opens showing hardware
schematic (Two And Gates Joined to
Create 3-input And)

electing the equation tab gives the truth

unction or equation

The truth table tab should give the

truth table for the function

The Karnaugh map is shown below

False or
Low
True or
High

ASSIGN PACKAGE PINS TO PORTS

Each VHDL signal name

(A, B, C, F) or NET must
be assigned to a FPGA
board pin connection
(location) or LOC.
Input signals are assigned
to switches and buttons
Output signals are
assigned to LEDs or the
7-segment display
NEXYS 3 Data Sheet:
www.digilentinc.com/Dat
a/Products/NEXYS3/Nexys
3_rm.pdf

ADD CONSTRAINTS FILE (UCF)

1. Right-click in
the Design Panel
(Upper left hand
side of screen.)
2. Choose New
Source from
pop-up menu

3. Select
Implementation
Constraints File
4. Enter
AND_3

When done
checking data
Click on Next>

ACCEPT SUMMARY

Check that this is

the correct file type
File Name you
Entered
Project Name

When done
checking data
Click on Finish

Working directory on
your computer or
Flashdrive
(Flashdrive is better)

EDIT UCF
1. Double-click AND_3.ucf

2. Assign as follows:

Input A to SW2 (V9),

input B to SW1 (T9),

input C to SW0 (T10),

output to the LED designated

(U16)
Debugging Tip: Sometimes the board expects the above in a different
format. If your files and simulations check out but the board does not
respond to switch settings, you will need to try the alternate format
given on the following slide.

KNOWN ISSUE
Please use the file NEXSYS3 MASTER FILE as a template.
Note, the Nexys 3 board will pick either form.
Try one and if it doesnt work try the other.
Input A
SW2
#NET "sw<2>"
LOC = "V9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32N_GCLK28,
Sch name = SW2
NET A"
LOC = "V9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32N_GCLK28,
Sch name = SW2
Or
NET A"
LOC = "V9" ; # | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32N_GCLK28,
Sch name = SW2
input B
SW1,
#NET "sw<1>"
LOC = "T9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32P_GCLK29,
Sch name = SW1
NET B"
LOC = "T9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32P_GCLK29,
Sch name = SW1
Or
NET B" LOC = "T9" ; #| IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32P_GCLK29,
Sch name = SW1
input C
SW0,
#NET sw<0>"
LOC = "T10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L29N_GCLK2,
Sch name = SW0
NET C"
LOC = "T10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L29N_GCLK2,
Sch name = SW0
Or
NET C"
LOC = "T10" ; # | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L29N_GCLK2,

GENERATE PROGRAMMING FILE

1. Open AND_3.vhd
2. Double-click Generate
Programming File
The interface will

Translate VHDL to netlist

Map design and
NOTE:
If, during the generate
optimize gates
process, ISE flags errors in
Place and Routes gate
your code, you must correct
them before the .bit file is
assignments to FPGA
created.
board
ISE may also flag warnings.
Creates .bit file
Only some warnings must
be corrected. For this course
you can usually ignore
warnings. Ask your TA for

UPLOAD .BIT FILE

1. Connect FPGA board
to computer with USB
cable.2. Turn board on.

3. Open Digilent Adept.

4. Browse to your work

folder.

Debugging Tip: If you have made

changes to your code and it does not
appear to have any affect on the how
the program works on the board, you
may not be uploading your file.
Always double check the directory
and the date\time label for the file.

UPLOAD .BIT (CONT.)

1. Select the file (AND_3.bit) for uploading by double-clicking on

2. Click Program to start up

loading the program

The .bit file is

programmed to
the FPGA board.

LAB 0 PROJECT A NOT, AND, OR

Create a new project. Name it Lab0A.

1.

Create the truth table for these three operations.

Simulate the VHDL module. Make stimulus inputs count
from 00 11, waiting 100 ns between each count.
Verify that your truth table corresponds with the
simulation output.
Create a UCF for Lab0B. Assign:

2.
3.

4.

5.

6.
7.

Write the VHDL that performs the NOT, AND, OR operations on two
input values.
Input signals: A and B
Output signal: F_NOT, F_AND, F_OR.

A to SW1, B to SW0
F_NOT to LD0, F_AND to LD1, F_OR to LD2.

Generate and download program file (.bit) to FPGA

Verify that the hardware works as expected based on your
truth table from #32.

TRUTH TABLES FOR NOT, AND, OR GATES

Inpu
ts

Output

F_NOT

Input Outpu
s
t
A B

F_AN
D

Input Outpu
s
t
A B F_OR
1 0 0

2 0 1

3 1 0

3 1 0

4 1 1

4 1 1

1 0 0

2 0 1

LAB 0 PROJECT B
NAND, NOR, XOR, XNOR, BUFFER
Create a new project. Name it Lab0A.

1.

Create the truth table for these five operations.

Simulate the VHDL module. Make stimulus inputs count
from 00 11, waiting 100 ns between each count.
Verify that your truth table corresponds with the
simulation output.
Create a UCF for Lab0B. Assign:

2.
3.

4.

5.

6.
7.

Write the VHDL that performs the NAND, NOR, XOR, XNOR and Buffer
operations on input values.
Input signals: A and B
Output signal: F_NAND, F_NOR, F_XOR, F_XNOR, F_BUFF.

A to SW1, B to SW0
F_NAND to LD0 ,F_NOR to LD1, F_XOR to LD2, F_XNOR to LD3, F_BUFF
to LD4

Generate and download program file (.bit) to FPGA

Verify that the hardware works as expected based on your
truth table from #34.

TRUTH TABLES FOR

NAND, NOR, XOR, XNOR, BUFFER
Inpu
ts

Outpu
t

Inpu
ts

Outpu
t

F_NO
R

F_XN
OR

Inpu
ts

Outpu
t

Inpu
ts

Outpu
t

Inpu
ts

Output

F_NAN
D

F_XOR

F_BUFF

LAB 0 PROJECT C DEMORGANS

LAWS
1.

Create a new project. Name it DeMorgan_Gates.

2.
3.

4.
5.

6.
7.

Write VHDL for a not, and, and or gates using only nand gates.
Input signals: X, Y for the three gates.
Output signals: F_NOT, F_AND and F_OR
(Review chapter 1 pages 26 to 32. (Especially Figures 1.15 and 1.16)

Create the truth table for all gates.

Simulate the gates. Make stimulus inputs count from 00 11, waiting 100 ns
between each count.
Verify that your truth tables correspond with the simulation output.
Create a UCF for the gates; Assign:

X to SW7

Y to SW6

F_NOT to LD7

F_AND to LD4

F_OR to LD0
Generate and download program file (.bit) to FPGA
Verify that the hardware works as expected based on your truth tables from #32.

DEMORGAN LOGIC GATES

F_Not <= A nand A

NOT Gate
F_NOT

F_AND

F_NOT

F_AND <= (A nand B) nand (A nand B)

AND Gate
A
F_AND
B
F_OR <= ?
OR Gate

A
B

F_OR
B

F_OR

LAB REPORT

Cover page:

Course Title
Lab Number, Letter
Team Names

VHDL Module
Black Box
Truth Table
Simulation Waveform
UCF

Project 0B:

VHDL Module
Black Box
Truth Table
Simulation
UCF

Project 0C:

Project 0A:

VHDL Module
Black Box
Truth Table
Simulation
UCF

Summary paragraph

Work completed
Any problems
Helpful Hints
Suggested
Improvements