Atul AES Presentation

Department of Electronics & Telecommunication
Engineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
Design & Implementation of 128 bit AES

Crypto processor using FPGA
By
Atul D.Narkhede
Under the Guidance of

Prof. U.A.Rane

Engineering
PROJECT OUTLINE
INTRODUCTION
ENCRYPTION
DECRYPTION
BLOCK DIAGRAM
RESULTS
CONCLUSIONS
REFERENCES

Engineering
Introduction
The crypto processor is dedicated microprocessor for carrying
cryptographic operations using various secure crypto graphical
standards and efficient algorithms.
We are interested to design and implement128 bit crypto
processor using Advanced Encryption Standard (AES) .
The physical development will be done using VHDL,
hardware description language.

Engineering
AES is an algorithm for performing encryption and the reverse
decryption, which is a series of well-defined steps that can be

followed as a procedure.
The original information is known as plaintext, and the encrypted
form as cipher text.
AES is one of the most popular algorithms used in symmetric key
cryptography.
Symmetric-key cryptography refers to encryption methods in which
both the sender and receiver share the same key or very less
commonly their keys are different, for this reason it counted in
symmetric ciphers.

Engineering
AES Encryption
and Decryption

Engineering
Add RoundKey
Encryption
Process
i=1
Byte Sub(State)
ShiftRow(State)
Mixcolumns(State)
Add round Key
i=i+1
I <Nr
Byte Sub(State)
ShiftRow(State)
Add round Key
K
E
y
S
C
H
E
D
U
L
E

Engineering
Add RoundKey (State, Invroundkey)
Decryption
Process
i=1
InvByte Sub(State)
InvShiftRow(State)
Mixcolumns(State)
Add round Key(state,Invround key)
i=i+1
I < Nr
InvByte Sub(State)
InvShiftRow(State)
Add round Key(state,Invround key)
K
E
y
S
C
H
E
D
U
L
E

Engineering
Hardware
PC with Xilinx ISE 7.1i
Xilinx Spartan III Development
Board XC3S400-4 PQ208C
PS/2 Input
4 x 20 Line LCD Display
Functional Description

Engineering
Sub-System Block Diagram

PS2
Keyboard
Interface
Program
Control
Logic
RAM
ROM
AES Core
LCD
Interfac
e

Engineering

Engineering
Block
Diagram

Engineering
Results
Image 1
Image 2
Project Setup
FPGA Kit (Spaten-3)

Engineering
Image 3
Image- 4
Initial Start up
AES in ASCII Mode

Engineering
Image-5
Image -6
Insert Character
Encryption of Data in HEX Mode

Engineering
Image- 7
Image- 8
Encrypted Data in ASCII Mode
Decrypted Data in HEX Mode

Engineering
Image 9
Original Data after Decryption
Image-10
Complete look

Engineering
Image-11
Image 12
Key Given in HEX Mode
Data Given in HEX Mode

Engineering
Image- 13
Encrypted Data in HEX Mode
Image 14
Encrypted Data as I/P

Engineering
Image- 15
Original Data after Decryption

Engineering
Conclusion
By using AES algorithms network processor can encipher and decipher the text by
using cipher key of size 128, 192,or 256 bits.
AES-128 implementation can be used in cryptographic accelerator Cards,
which helps in real time encryption process of servers at the time of client
authentication and symmetric encryption process,
which reduces load of CPU usage.

Engineering
Applications
Secure Communication
ATM
DVD Content
Secure Networks
Secure Storage
Confidential Corporate Documents
Government Documents
FBI Files
Personal Storage Devices
Person Information Protection

Engineering
References
[1] William Stallings Cryptography and Network Security Principles and Practices, Fourth
Edition,, November 16, 2005
[2] Haiyong Xie, Li Zhou, and Laxmi Bhuyan Architectural Analysis of Cryptographic
Applications for Network Processors.
[3] Spartan-3 Generation FPGAs :- The Ultimate Low-Cost Applications Platform.
[4] Kris Gaj and Pawel Chodowiec Hardware performance of the AES finalists - survey
and analysis of results, George Mason University
[5] www.en.wikipedia.org/advanced encryption standard
[6] FIPS 197, Advanced Encryption Standard (AES), November 26, 2001
http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

Engineering
References
[7] J. Daemen and V. Rijmen, AES Proposal: Rijndael, AES Algorithm Submission,
September 3, 1999
http://www.esat.kuleuven.ac.be/~rijmen/rijndael/rijndaeldocV2.zip
[8] AES page available via http://www.nist.gov/CryptoToolkit.
[9] Computer Security Objects Register (CSOR):www.//csrc.nist.gov/csor
[10] Gentre Graham & David Leifker, VHDL AES128 Encryption /Decryption Senior Project
Report, May 9th 2004
[11] Rajender Manteena, A VHDL Implementation of the AES-Rijndael Algorithm A thesis,
March 23rd 2004

Atul AES Presentation

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Atul AES Presentation

Uploaded by

Copyright:

Available Formats

Department of Electronics & Telecommunication

Design & Implementation of 128 bit AES

Under the Guidance of

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

AES is an algorithm for performing encryption and the reverse

decryption, which is a series of well-defined steps that can be

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Add RoundKey (State, Invroundkey)

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Sub-System Block Diagram

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

FPGA Kit (Spaten-3)

Department of Electronics & Telecommunication

AES in ASCII Mode

Department of Electronics & Telecommunication

Encryption of Data in HEX Mode

Department of Electronics & Telecommunication

Encrypted Data in ASCII Mode

Decrypted Data in HEX Mode

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Key Given in HEX Mode

Data Given in HEX Mode

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

Department of Electronics & Telecommunication

You might also like