Professional Documents
Culture Documents
Devices
High End Scanners
Agenda
The Genesis of
Digital Capture
- Remote Sensing
Analog capture
Required film return
Slow
1970s
- CCD invented
Graphical computing
Digital communications
The Internet
Consumer capture devices emerge
Scanners
Digital
Cameras
Digital
Camcorders
Convenience
Digital enables instantaneous interchange
Affordability
No photo processing fees
Ability to leverage semiconductor economies of scale
Market Forecasts,
Trends, and Key
Conclusions
2000
28,676
1,175
8,339
3,085
3,904
4,044
431
6,179
5,170
2,205
6,144
69,351
2001
29,218
2,469
7,683
2,512
5,426
6,254
229
7,488
6,927
2,393
6,841
77,438
2002
28,710
3,813
7,313
1,875
6,789
8,507
136
8,640
6,117
2,630
7,435
81,964
2003
28,856
6,358
6,549
1,186
8,503
10,791
103
9,728
5,502
2,818
7,828
88,223
2004 CAGR(%)
28,609
0.5
10,732
93.5
6,177
-6.7
924
-22.4
10,465
28.7
12,232
37.8
79
-34.2
10,331
16
5,458
7.8
3,383
17.8
8,286
7.5
96,677
9.2
Units (M)
Worldwide Scanner
Shipment Forecast
20
18
16
14
12
10
8
6
4
2
0
Scanner
2000
2001
2002
Year
2003
2004
High-end Scanners
Analog Camcorder
Digital Camcorder
Security Cameras
Digital Still Cameras
PC Cameras
Toys
Cell Phones
PDAs/Handhelds
Automotive
Biometric
2000
8,685
6,107
9,600
12,700
9,000
2,700
100
40
20
50
2001
8,142
8,056
12,100
18,100
15,000
3,800
900
220
75
275
2002
7,990
9,751
15,300
23,350
22,000
5,500
3,100
1,100
225
730
2003
7,755
10,959
19,400
29,100
30,000
7,800
17,800
2,400
1,550
1,500
Digital Capture
Basics
CCD (Eye)
CCD (Eye)
CCD (Eye)
CCD (Eye)
CCD (Eye)
CCD (Eye)
R
G
B
CCD (Eye)
1010101
0010001
A/D
Converter
Dots Amazing!
The captured digital images are comprised of
many tiny colored dots
These dimensions
define the resolution
of the image captured
Zooming In
Each pixel is comprised of three sub-pixel elements: one each for
Red, Green, and Blue, each respectively represented by separate
binary (digital) values
Digital Image
Processing
Contrast enhancement
Shadow enhancement
Sharpness enhancement
Chroma key compositing
Graphic overlay
Implementation Examples
CMOS
Are active devices that read out their charge via transistors
placed in each pixel
Uses CMOS manufacturing process
Courtesy: www.pctechguide.com
Digital Scanner
System Analysis
and Block
Diagrams
Image Processing
- DCT/IDCT, color space conversion, compression, etc.
- Gamma/color correction, half-toning, brightness,
contrast, sharpness, etc.
System Controller
System
Control
Microcontroller
System Transport
- DMA access to system memory resources, PCI, local bus, dual-port memories
High-speed
Transport
PHY
- LVDS, BLVDS
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
Digital
Memory
Mixed Signal
uP or uC
FLASH
DRAM
Programmable
SRAM
IP Block
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
CCD
Creates analog RGB image
representation of object
in focus
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
A/D Conversion
Image
Processing
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
A/D Converter
Converts analog RGB values to
sampled digital values
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
CCD Interface
Buffers and sorts sampled
digital RGB values
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
System Control
Image
Processing
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
System Controller
Provides system level hardware
interface between all functional
blocks
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
Image Processing
Image
Processing
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
Image Processing
Provides improved system level
performance via hardware
accelerated image processing
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
Microcontroller
Orchestrates proper and timely
system interactions between
hardware and software
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
Memory Control
Image
Processing
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
Memory Controller
Provides system level interface
signals for accessing memory
devices and resources
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
High-Speed Transport
Image
Processing
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
High-Speed Transport
Image
Processing
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
High-Speed Transport
Image
Processing
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
LVDS/BLVDS I/O
Provides high-speed serial
transport of captured and or
streaming images
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
Digital Image
Image
Processing
A
Digital
CCD /
RGB
D
CCD
I/F
Optional
Digital
Encoding
PHY
High
Speed
I/O
System
Controller
Digital
Memory
Controller
uC
ROM
Digital RGB
MPEG, JPEG, TIFF, etc
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
FLASH
DRAM
SRAM
Lens
CCD
A
/
D
Digital
RGB
Optional
Digital
Encoding
High
Speed
I/O
System
Control
CCD I/F
PHY
Memory
Controller
ROM
FLASH
uC
DRAM
SRAM
Digital
Memory
Mixed Signal
uP or uC
Programmable
IP Block
Digital
Xilinx Solutions
High Volume
Low Cost
Virtex, Virtex-E,
Virtex-EM, Virtex-II,
Virtex-II Platform FPGA
Low Power
Low Cost
XC9500, XC9500XV,
XC9500XL, CoolRunner
XPLA3
Port B
Differential I/O
400 Mbps
LVDS
Bus LVDS
LVPECL
Dual-Port
4Kbit
BRAM
Block RAM
Up to 64Kbits
200 MHz
CL DLL
I
O B
B R
I A
O M
B
I
O B
B R
I A
O M
B
IOB
IOB
IOB
IOB
IOB
IOB DLL CL
I
CLB CLB CLB CLB CLB CLB B O
R B
A I
CLB CLB CLB CLB CLB CLB M O
B
I
CLB CLB CLB CLB CLB CLB B O
R B
A I
CLB CLB CLB CLB CLB CLB M O
B
I
O B CLB CLB CLB CLB CLB CLB
B R
I A
O M CLB CLB CLB CLB CLB CLB
B
CL DLL IOB IOB IOB IOB IOB IOB
System I/O
19 signaling standards
Chip to Backplane
Chip to Memory
Chip to Chip
CLKIN
CLKFB
RST
I
O
B
I
O
B
DLL CL
B
R
A
M
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
2ns
Spartan-IIE Technology
2n
2ns
CLB Tiles
Fast, predictable
interconnect
Memory Controller IP
Content Addressable
Memory (CAM)
DDR-SDRAM Controller
Quad-Data-Rate SRAM
Interface
Single-Port Block Memory
Registered single port
RAM
Registered ROM
Dual-port Block Memory
200MHz ZBT SRAM
Interface
SDRAM Controller
MicroBlaze
32-bit fully synthesized RISC processor
Fast
Twice the performance at half the logic area vs. competition
Timer/Counter Block
Watchdog Timer/Timebase
Interrupt Controller
16550/16450/Lite UART
ZBT Memory Controller
SRAM Controller
Flash Memory Controller
* Licensed for a fee
IIC*
SPI*
Ethernet 10/100 MAC*
More to come
Xtreme DSP
Industry first System Generator for Simulink bridges gap
between FPGA and conventional DSP design flows
Unique constraint-driven Filter Generator allows
optimization between performance and cost
Power estimator tool (Xpower) for power-sensitive DSP
implementations
Eleven optimized DSP algorithms (cores) that cut
development time by weeks
DSP features added to ChipScope ILA tool dramatically
accelerate hardware debugging time
Video/Image Processing IP
Inverse Discrete Cosine
Transform (IDCT)
1-D Discrete Cosine
Transform
2-D DCT/IDCT Forward &
Inverse Discrete Cosine
Transform
JPEG CODEC
FastJPEG Color Decoder
Fast JPEG B/W Decoder
2D FIR Filter
2D FFT
RGB2YCrCb
YCrCb2RGB
RGB2YUV
YUV2RGB
System
I/O I/O
User
Designed
A
Digital
CCD / RGB
D
Dual
Port
Buffer
Block
RAM
Memory
Memory
FIFO
System
Control
ROM
Controller
Mixed Signal
uP or uC
FLASH
Distributed
Buffer
MemoryRAM
Programmable
uC
IP Block
DLL
DLL
Digital Display
Controller
Analog Display
Controller
Microcontroller
SRAM
DLL
High Speed
I/O
DES
3DES
FLASH
SRAM
Sub-System
Controller
Controller
Controller
System I/O
User Designed
I/O
DLL
PHY
Clock Mgmt
ROM
Digital
High
Speed
PCI
Bus
DCT
Encoder
&
IDCT
Encryption
JPEG
Storage
Nonvolatile
Controller
Storage
DRAM
Controller
I/O
User System
Designed
I/O
User
Syste
m I/O I/O
Designed
Image Processing
LVDS, BLVDS
LCD
DAC
Compact
FLASH
Hard Disk
DRAM
Digital
TV/CRT
Xilinx CPLDs
XL9500 Families
High Performance
Low Cost Solution
CoolRunner Family
Lowest Power
Highest Reliability
Voltage flexibility
Summary
Digital scanners are one of the more popular consumer
devices
Wide acceptance in all geographies
Xilinx fit
Primarily used for interface between ASSP chips/chipsets
For external connectivity - Memory, USB, IEEE-1394