Major Project

Presentation

Designing and
development of forward
error correction logic in
VHDL.
By
Mentor Prof. S. Choudhoury

Ishan Upadhyay-R790211019
Abhipraiya
Bhatnagar-R790211002
Mar 2012

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Content
1. Introduction

2. Objective
3. Literature review
4. Block diagram
5. Timeline
6. Detailed component list/If any hardware
7. Detail software tools
8. Methodology
9. Outcome
10.Future plan
11.Conclusion
12.References
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Introduction
Data communication basically involves transfers of data from one
place to another or from one point of time to another.
Error may be introduced by the channel which makes data unreliable
for user.
In doing so there may be situations that error may be encountered in
the channel due to various factors like Electromagnetic Interferences,
Cross talk and Bandwidth limitation etc.
Hence we need different error detection and error correction
schemes.

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Objective
1. Errors introduced by the channel should be detected at the receiver
end.
2. Designing of turbo code algorithm .
3. Implementation of code using VHDL and burning it into Spartan-6
kit.
4. Correcting the error using FEC.

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Literature review
Turbo codes achieve performance near the Shannon limit.
Standard sequential VLSI implementation of turbo decoding requires
many iterations and incurs a long latency, which cannot be tolerated
in some applications. A novel parallel VLSI architecture for turbo
decoding is described,
comprising multiple SISO elements,
operating jointly on one turbo coded block, and
a new parallel interleaver.
Latency is reduced ten-fold and more and throughput is increased up
to eight-fold relative to sequential decoders, using the same area of
silicon, and achieving the same coding gain.
The parallel architecture scales favorablylatency and throughput
improve with growing block size and chip area.

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Block diagram
Turbo Encoder

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Turbo Decoder

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TIMELINE
PHASE I-We perform the comparative study between different FECs
like Shanon Fanon, Hoffmann, Cyclic, Convolution, Turbo Coding. (23 weeks)
PHASE II-Selection of best code is done for Forward error correction
and learning basic function of Spartan-6 kit.(2-3weeks)
PHASE III-Implement the code using VHDL programming and burning
code on the Spartan-6 kit.(1-2 weeks)
PHASE IV-Removing the problem in the code.(1-2 weeks)
PHASE V-Finally the perfect code for Forward error correction is
implemented on FPGA Spartan-6 kit.(3-4 weeks)

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Detail software tools

Spartan-6 FPGA Board & kit.
Software required- Project Navigator, Xilinx Support

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Uniqueness

Methodology

Turbo codes:1. In Turbo encoding scheme

standard
is
a
parallel
concatenated
convolutional
code and one interleaver.
2. The function of the interleaver
is to take a block of N-bit data
and produce a permutation of
the input data block.
3. The performance of a Turbo
code depends critically on the
interleaver structure. The
basic Turbo coding rate is 1/3.
4. It
encodes
an
N-bit
information
data block in to a
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Methodologycont..
1. A turbo decoder consists of two
decoders separated by an interleaver
that permutes the input sequence.
2. The decoding is an iterative process in
which the so-called extrinsic information
is exchanged between decoders.
3. Each Turbo iteration is divided in to two
half iterations.
4. During the first half iteration, decoder 1
is enabled. Likewise, during the second
half iteration, decoder 2 is enabled.
5. This iterative process repeats until the
decoding has converged or the
maximum number of iterations has been
reached.

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INPUT
X1

X2

X3

X4

X5

X6

X7

X8

X9

X10

X11

X12

X13

X14

X15

Odd-even interleaver output

Encoder output without interleaving
X1

X2

X3

X4

X5

X6

X7

X8

X9

Y1

Y3

Y5

Y7

Y9

X10 X11 X12 X13 X14 X15

-

Y11

Y13

Y15

Encoder output with row-column interleaving

X1

X2

X3

X4

X5

X6

X7

X8

X9

Z6

Z2

Z12

Z8

X10 X11 X12 X13 X14 X15

Z4

Z14

Z10

Final output of the encoder

Y1

Z6

Y3
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Z2

Y5

Z12

Y7

Z8

Y9

Z4

Y11 Z14 Y13 Z10 Y15

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Channel Used for transmission

Additive White Gaussian Noise Channel (AWGN)
The modifiers denote particular characteristics as below,
'Additive' because it gets added to signal noise that might be intrinsic
or extrinsic to the information system.
'White' refers to idea that it has even power across the frequency
band of the information system. It is an analogy to the color white
which has uniform emissions at all frequencies in the visible
spectrum.
Gaussian because it has a normal distribution over the time domain
with an average time domain value of zero.

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Step wise implementation

1. First Simulink model for turbo encoder and Turbo decoder is
developed
2. The VHDL coding is made and verified
3. The HDL codes are synthesized by Xilinx Support Design
Complier
4. Finally the physical design is implemented on Spartan-6 FPGA
Board & kit

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Outcome or Result
Various forward error correction techniques have been studied and compared.
Among all the FECs, Turbo code has been found to be the most suitable code
because of the low coding complexity and high coding rate etc.
Bit Error Rate:
0.0368951613 @ iteration 0 (no decoding)
0.0027355688 @ iteration 1
0.0001380629 @ iteration 2
0.0000722789 @ iteration 3
0.0000255319 @ iteration 4
0.0000212947 @ iteration 5
Signal-to-noise ratio: 5.1 dB

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Xilinx implementation image

Interleaver

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Interleaver

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Encoder

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Encoder

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encoder

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Future plan

At this stage our future plan is to design and develop the Forward Error
correction logic circuit using VHDL programming on FPGA kit and
observe the working of the Turbo code derive system.

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Conclusion
Turbo code performance simulation on AWGN Channel
1. Number of iterations of the Turbo code performance
With the increase of the signal to noise ratio, increasing the number of iterations will make
the bit error rate is drastically reduced, but when a certain number of iterations is
reached, and then increase the number of iterations is also not significantly improve
the BER.
2. Encoding rate of Turbo code performance
The puncturing process may be useful, Seen by the simulation results in the case of the
same SNR, the code rate is 1/3 of the code having a higher bit error rate
performance than the code rate is 1/2 code. Because the bit rate of 1/2 Turbo Code .

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References
http://www.google.com
[2] University of South Australia, Institute for Telecommunications
Research, Turbo coding research group.
http://www.itr.unisa.edu.au/~steven/turbo/.
[3] S.A. Barbulescu and S.S. Pietrobon. Turbo codes: A tutorial on a
new class of powerful error correction coding schemes. Part I: Code
structures and interleaver design. J. Elec. and Electron. Eng.,
Australia, 19:129142, September 1999.

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THANKYOU

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