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Lecture 1
Review of CS 161
MIPS ISA
Stage 5
PC
Instruction
Memory
(Imem)
Registers
Stage 1
Stage 2
ALU
Stage 3
ALU
IM
DM
Reg
Data
Memory
(Dmem)
Stage 4
Time
IFtch Dcd Exec Mem WB
IFtch Dcd Exec Mem WB
IFtch Dcd Exec Mem WB
IFtch Dcd Exec Mem WB
Program Flow
I
n
IM Reg
DM Reg
Load
s
IM Reg
DM Reg
t Add
r.
IM Reg
DM Reg
Store
O
IM Reg
DM Reg
Sub
r
IM Reg
DM Reg
d Or
e
r
(right half highlighted means read, left half write)
ALU
ALU
ALU
ALU
time
Reg
Reg
IM
DM
10
12
14
Reg
DM
Reg
Reg
ALU
IM
ALU
IM
ALU
Reg
IM
DM
ALU
IM
ALU
Reg
DM
Reg
Reg
IM
ALU
Reg
DM
Reg
16
18
20
Time
IFtch Dcd Exec Mem WB
IFetchDcd Exec Mem WB
IFtch Dcd Exec Mem WB
IFtch Dcd Exec Mem WB
IFtch Dcd Exec Mem WB
IFtch Dcd Exec Mem WB
Program Flow
ILP = 2
Time
IFtch Dcd Exec Mem WB
Exec
IFtch Dcd Exec Mem WB
Exec
IFtch Dcd Exec Mem WB
Exec
Program Flow
EX: Itanium