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VLSI DESIGN
FOR
SECURITY
Guided By,
Dr. AJAYAN K R
Associate Professor
ECE Dept.
CET
Submitted By,
ASHA SATHEES
Roll No: 03
M2 MTV
CONTENTS
INTRODUCTION.
VLSI
RECONFIGURATION
SECURITY.
LEON2
PROCESSOR
CONCLUSION
INTRODUCTION
A critical
reliability.
Reconfiguration
Hardware
Nowadays
Such
co-
processing boxes.
Hardware
Recently
CONT
Reconfigurable
computing technologies.
Supply chain risk attack model.
VLSI encryption/locking.
o Combinational logic locking.
o Finite state machine locking.
Obfuscation
Key propagation
Path analysis
Graph isomorphism
RECONFIGURATION BASED
VLSI DESIGN FOR SECURITY
CONT
LEON2 PROCESSOR
LEON2
FE
D Q
DE
RF
D Q
EX
D Q
ME
M
DM
D Q
W
R
CONT
Possible attack and defense schemes:
On computational integrity.
Hardware Trojans that compromise computational integrity.
Code injection hardware Trojan (shaded in red) including a Trojan ROM, a group of
multiplexers, and a trigger logic module.
CONT
Reconfigurable instruction decoder for instruction set
randomization.
Evaluation
CONT
On data confidentiality.
Memory access Trojans
Attack targets of five unauthorized memory access hardware Trojans in a LEON2 processor.
CONT
1) injecting a memory access instruction;
2) injecting memory access request signals including a memory
address and an Address Space Identifier ;
3) injecting memory access request signals including a memory
address while tampering the supervisor signal;
4) injecting memory access request signals including a memory
address after tampering the Process State Register;
5) injecting memory access request signals including a memory
address after tampering the PSR directly.
CONT
Reconfigurable memory access module against illegal memory access
Obfuscated memory access logic (shaded in blue) including memory access instruction decoding
logic, WRPSR decoding logic, PSR, supervisor signal logic and ASI logic.
CONT
Evaluation.
CONCLUSION
Proposed
system includes
CONT
Achieve
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