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PRESENTATION ORAGANISATION
MOTIVATION
PROPOSED SYSTEM
HYBRID RTL SCHEMATIC DIAGRAM
RSA ALGORITHM
SEA ALGORITHM
SIMULATION RESULTS
CONCLUSION AND FUTURE WORK
REFERENCES
MOTIVATION
Today more and more sensitive data is stored digitally. Military
data , Bank accounts, medical records and personal emails are
some categories where datas must be secure.
The use of systems with increasing complexity, which usually
are more secure has a low throughput rate and more energy
consumption.
Protecting the digital data through encryption using tools and
external codes are highly cost effective and also results in
performance degradation.
now
either
symmetric
cryptographic
processor
or
leads
to
the
basis
for
this
project
to
exploit
the
PROPOSED SYSTEM
For implementation, an Asymmetric RSA (Rivest-ShamirAdelman) cryptography and a symmetric light weight SEA
(Scalable
Encryption
Algorithm)
cryptography
are
RSA
SEA
Asymmetric
Symmetric
Key used
Public key
Secret key
Type
Stream cipher
Block cipher
Security
High
Low
Speed
Low
High
Scalability
No
Yes
More
Less
different
Same
Modular Arithmetic
Cryptanalysis method
product factorization
no known method
PROPOSED ARCHITECTURE
HYBRID
RW
RSA
Enc
Data IN
Random
Logic
Selection
En
KEY RSA
Data
Mux 1
HYBRID DOUT
SEA
Enc
Address
RSA Dout
SEA Dout
KEY SEA
Key
Mux 2
En
KEY HYBRID
HYBRID
RSA
Dec
Data OUT
Mux 3
SEA
Dec
RW
Enc Data
Memory
Address
Key
Address
En
Look Up
Table
HARDWARE DESCRIPTION
Controller Unit
32
Reconfigurable
Cryptographic
Unit
Random Logic
and selection
Unit
Memory
Cell
Instruction
LUT
I/O interface
Registers
Internal Bus
System Bus
32
RSA ALGORITHM
P&Q (Two large prime numbers are
choiced)
N=P*Q
CT to receiver
Check gcd(3,20)=1
Compute d=7
Therefore the public key is (n, e) = (33, 3) and the private key is (n, d) = (33, 7).
Now say we wanted to encrypt the message M=7
C = Me mod n
C = 73 mod 33
C = 343 mod 33
C = 13
So now the cyphertext C has been found. The decryption of C is performed as
follows.
M' = Cd mod n
M' = 137 mod 33
M' = 62,748,517 mod 33
M' = 7
56
Frequency
177 MHZ
38
8.410 ns
Combinational functions
56
Clock set up
5.649 ns
Total pins
17
68.55 mW
47.25mW
21.20mW
SEA ALGORITHM
SEA Mapping
Combinational
ALUTs
368
Frequency
330.17 MHZ
Total pins
240
6.091 ns
15.969 ns
9.333ns
Worst case th
2.636 ns
Clock set up
2.945 ns
322.2
mW
303.05
mW
27.80
mW
353
88.97 MHZ
7.98 ns
15.12 ns
9.271ns
Worst case th
2.636 ns
Clock set up
11.240 ns
701
99
Frequency
78.05
mW
47.37m
W
31.19
mW
REFERENCES
[1]. Jun-Hong Chen, Ming-Der Shieh, Member, IEEE, and Wen-Ching Lin (2010). A HighPerformance Unified-Field Reconfigurable Cryptographic Processor in the proceedings of
IEEE transactions on very large scale integration (vlsi) systems, vol. 18, no. 8.
[2]. Neil Smyth, Mire McLoone and John V McCanny (2005). Reconfigurable Processor for
Public-Key Cryptography in the proceedings of IEEE.
[3]. Qiang Liu Fangzhen Dong Tong Xu Cheng. (2004). A Regular Parallel RSA Processor in
the proceedings of the 47rh IEEE International Midwest Symposium on Circuits and Systems
in the proceedings of IEEE
[4]. Jun-Hong Chen, Ming-Der Shieh, Member, IEEE, and Wen-Ching Lin (2010). A HighPerformance Unified-Field Reconfigurable Cryptographic Processor in the proceedings of
IEEE transactions on very large scale integration (vlsi) systems, vol. 18, no. 8.
RSA
processor
for
encryption
and
Decryptio
in
the
THANK YOU