Basic VLSI Design

Introduction to VLSI design

Text Book: Introduction to
VLSI circuits and System by
Uyemura
Grading:
Homework +
Layout+
Simulation 15-30
%
Midterm+ Final
70-85%

ch1-2

Taiwans Leading: IC Industry

IC: Integrated
Circuits
Global Ranking

Related Industry

Information Technology
Hardware
Business Volume: US$128
billion

Unique
Vertically
Integrated
Supply
Chain and
Business
Model

Communication Industry
Business Volume:US$24.4
billion

Automobile Industry
Business Volume:US$12.8
billion

Current Status of
Taiwan IC
Industry

Unit: Thousand USD

(1USD=30NTD)

No. 2 in IC Design
Global share: 20.3%
No. 1 in IC Foundry
Service
Global share: 69.3%
No. 2 in DRAM
Manufacture
Global share: 19.0%
No. 1 in IC Packaging
Global share: 47.9%
No. 1 in IC Testing
Global share: 52.3%

Business volume: US$53.8

billion
Number of companies: 325

3 3

2014
(
)

IC

17,559

18.9%

30,714

73.4%

1 IC 2
50%

Taiwan Semiconductor Industry

IC
Manufactur
e

IC Design
Mediatek
Morning Star
Novatek
PHISON
Realtek
Himax
Richtek
GUC
Ilitek
Raydium
Sitronix
Etrontek
Sunplus
Faraday
Silicon Motion
PixArt
ELAN
Nuvoton
ALi

IC Foundry service
TSMC
UMC
VIS

RAM Manufacture
STSP
Nanya
ProMOS
Winbond
Powerchip
Rexchip
MXIC

Packaging

Testing

ASE
SPIL
PTI
Greatek
FATC
OSE
Walton

ASE
King Yuan
PTI
chipMOS
SPIL
Ardentec
Sigurd
FATC
Walton
YTEC

Note: companies marked in

red only performs packaging
and testing.

Source MIC, 2012

5 5


1.6
GDP 12%

46%
1,200

(100-104 )
99 188

IC -- IEK, 2014
7000

4C
MG +

6000

5000

4000

3000
2000

4115

3856

4811

5425

1000
0
100

101

102

103(e)

104(f)

(3D)

(ReRAM) /

/
(MEMS)

CMOS

(OCT)/

(PV) /

LED
/

IGBT

(SiC)/ (GaN)


.
.IDM
IDM

. .IC
IC

IC

IC

(
Global Foundries)

(
)

. .IC
IC

.
.

NPIE (2014


25

20

15

10

44

3.6

39

3.5

34

3.4

29
24

3.3

19

3.2

14

3.1

3.0

4
-1

2008 2009 2010 2011 2012 2013 2014

2.9

Beyond Hospital Healthcare for Medical

Electronics
Ubiquitous healthcare on the web
anytime and anywhere!

Develop miniaturized wearable/implantable

medical wireless sensors/actuators for
beyond-hospital healthcare.
11

NPIE Ultra Low Power Chip and System

Low Voltage RISC

(0.23V@375KHz, TSMC 180nm)

Low Voltage H.264 Decoder (0.5V@40MHz, UMC90nm)

16K
B
ROM

N8
8KB
SRAM

H.264
Encoder

BIU
AMBA AHB

Low Voltage SRAM

(32K bits, 0.13V@100KHz, UMC 90nm)

1Mb
1Mb
Frame
Buffer
Buffer

H2P
H2P
Bridge
Bridge
I22C,
timer,
timer,
sys_ctrl
sys_ctrl

Image
Image
Grabbe
Grabbe
rr

Mem
Mem
Ctrl

SM
SM
II

Ultra Low Voltage Video SoC

(0.4V@2MHz, TSMC 65nm) 12

Applications of Ultra Low Power Design

Vital Sign Detection

Wireless capsule endoscopy

Digital Plaster

Mobile Body Sensing

13

Human Senses

Sight

Heari
ng

Though
t

Touc
h
Smel
l

Chinese Opera Makeup

Tast
e

ch1-14 1

LEGO MINDSTORMS NXT

Touch Sensor

Voice Sensor

Ultrasound Sensor

Light Sensor
ch1-15 1

VLSI Design

 Iphone

ch1-17

VLSI Design

ch1-18

VLSI Design

VLSI Design

ch1-20

ch1-21

Hardware courses

Logic Design :
Gate level Design

:
High Level Design with Verilog

Computer Architecture:
Architecture (Register Level) Design

Basic VLSI Design:

Transistor + Layout Design
ch1-22

Chip Design & Manufacturing Flow

IC Fabrication
Idea
Wafer
(hundreds of dies)

Architecture Design

Sawing & Packaging

Block
diagram

Final chips

Circuit & Layout Design

Testing

Layout
customers
Bad chips

Good chips
ch1-23

A Simple Example

Functionality
One-bit binary full-adder

Technology

A
B
C

Sum
Full-adder
Carry_out

1 m n-well CMOS technology

Speed
Input to output delay < 5 ns

Area
< 3000 m2

Power Dissipation
< 1 mW at 5 volts and 200 MHz

Boolean Description
Sum = A B C
= ABC + ABC + ABC + ACB
Carry_out = AB + BC + CA
(majority function)

ch1-24

Logic Design

x = Carry_out

Sum = A B C
= ABC + ABC + ABC + ACB
Carry_out = AB + BC + CA
(majority function)

# of 1s
In A, B, C

Carry_out

Sum

(A+B+C) x => exactly one of A, B,C is 1

Logic minimization trick:

The carry_out signal is used to realize the function of signal sum
in order to reduce the overall circuit size.
Todays logic synthesis tools (such as Design Compiler) incorporating
some advanced algorithms, is able to perform automatic logic minimization.
ch1-25

Transistor-Level Schematic

x
x
y

x = (AB+BC+CA)
y = (A+B+C) x + ABC)

Technology

mapping

Many simple AND OR gates are merged into a complex gate (or a
cell in the cell library)

Transistor

aspect ratio

pMOS (W/L) is usually larger than nMOS (W/L), e.g., 2:1

ch1-26

Initial Layout

Ratio of
channel widths
2:1

Post-layout

SPICE simulation

includes the parasitic resistance & capacitance

is more accurate than the pre-layout simulation (pre-sim)
ch1-27

I/O Simulation Waveforms

Sum
C (Carry_in)

Propagation time t PHL or t PLH as defined above

Low-to-high propagation time t PLH = 8.2 ns !

Got to go back to optimize the design !!!

ch1-28

Optimized Layout
Propagation Delay < 5 ns !

Transistor Sizing
changes the aspect ratios (W/L) of selected transistors
A larger aspect ratio may lead to a higher speed

Wire Sizing is also more recently proposed

ch1-29

Various Levels of Simulation

HDL

Simulation

Behavioral HDL simulation

Register-Transfer-Level (RTL) simulation
Gate-Level simulation
Switch-Level

Simulation

Transistor-Level

Simulation

(e.g., PowerMill)
Circuit

Simulation

(e.g., SPICE)

ch1-30

Automatic Layout

Cell-based Design

[Brodersen92]
ch1-31

Example Layout

SRAM

Routing Channel

SRAM

Data paths

Standard cells

Video-encoder chip
[Brodersen92]
ch1-32

Design Flow and Defect Level

# bad chips
Defect Level: -------------------------spec.
(
# )total shipped chips
The quality of test patterns dictates the defect

design flow

layout

test
patterns

manufacturing

ch1-33

Basic VLSI Design

Presents

modern CMOS logic circuits,

fabrication, and layout in a cohesive
manner that links material together with
the system-level considerations.

ch1-34

Basic VLSI Designs

Illustrates

the top-down design

procedure used in modern VLSI chip
design with an emphasis on variations
in the HDL, logic, circuits, and layout.
See the tradeoffs that occur at all levels
of the design hierarchy. To compare
different solutions to a problem, and
learns how design choices affect the
overall outcome.

ch1-35

End of Introduction
!

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Design Rule: spacing, width

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ch1-48

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ch1-50

Typical SOC Design

CF/SMC/MMC

LCD
Controller

Bluetooth
PVCI

PLL

ROM/Flash/
SRAM/IO
Controller

Arbiter/
Decoder

DMA
Controller

SDRAM
Controller

ARM
Core

Bridge

AHB

Power
Management

SSP/SPI
Microwire

DSP
Core
Code
Memory

Embedded
Memory

Data
Memory

MMU
Cache

Interrupt
Controller

APB

Timer

RTC

I2 S

GPIO

UART/
IrDA
ch1-51

ch1-52

Go Back
ch1-53