Class D Power amplifier

-----using ADS
Song lin @utk June30

Outline
Why select Class D?
Compare different device
Simple Class D architecture
Load-pull to give out Zout
Matching and simulation results of
ideal narrow band Class D PA
Broad band matching

Why Class D?
Class D PA works in the switching mode, with a
square wave voltage and a half wave rectified
sine wave of current.
In its ideal switching mode,
when Vds<>0, Ids=0;
when Ids<>0,Vds=0.
Class D PA can achieve very high frequency
close to 100%. Although it is very nonlinear,
we still can use the LINC technique to kill the
IMD product.

Two kinds of Class D PA

Compare the device(I)

For high frequency, ----- f max the higher the better
For high on/off switching speed,----- t sd the shorter
the better
For high efficiency, the on-resistance of a switching
device must be as low as possible to minimize the
power dissipation in the switches during the positive
half cycle.----- Rs is the smaller the better.
For high Power output, ----- BV(beake down voltage)
the higher the better
For high Gain, -----g m the bigger the better
I ds
For power dissipate,----the small the better

Compare the device(II)

Conclusion:

Also for the wide band application, we should

chose the component whose Zout and Zin has
very little variety in some frequency range.
I suggest to use the MRF282SR1.-----N-channel
Enhancement-Mode Lateral MOSFETs

Basic Class D PA architecture

Sample
Class D
Amplifier

Input
Bias Port

Port
OutBias
Num=4

Output
Bias Port
Do not delete
this port.

VD_F ET1
2

1
T1

C
C3
C=1.0 uF

GaAsF ET
FET1
Area=10
Trise=

Output
Port

vds1
3

C
C4
C=1.0 uF
GaAsFET
FET2
Area=10
vds2
Trise=

1
T2

Do not delete
this port.

I_Probe
ID_FET1

Do not delete
this port.

Input
Port
Port
Input
Num=1

Port
InBias
Num=3

TF3
TF1
T1=1.00
T2=1.00

I_Probe
ID_FET2
Statz_Model
Generic_GaAsFet
Trise=
Imelt=

TF3
TF2
T1=1.00
T2=1.00

vout1
SLC
SLC1
L=20.0 nH
C=1.750 pF

Port
Output
Num=2

Do not delete
this port.

Load Pull to give out Zout

One Tone Load Pull Simulation;
output power and PAE found at
each fundamental load impedance
I_P robe
Is_low

I_P robe
Is_high

Vs_low
V_DC
SRC2
Vdc=Vlow

Specify desired Fundamental Load Tuner coverage:

s11_rho is the radius of the circle of reflection coeffi cients
generated. However, the radius of the circle will be
reduced if it would otherwise go outside the Smith Chart.
s11_center is the center of the circle of generated reflection coeffi cients
pts is the total number of reflection coeffi cients generated
Z0 is the system reference impedance
s11_rho is the radius
Var VAR
and s11_center is the
E qn
SweepEquations
center of the circle.
s11_rho =0.35
(But this is just a
s11_center =-0.65 +j*0.0
static drawing.)
pts=100

L
L2
L=1 uH
R=

L
L1
L=1 uH
R=

Vs_high
V_DC
SRC1
Vdc=Vhigh

Z0=50
I_Probe
Iload

InBias
Input

P_1T one
PORT 1
Num=1
Z=50 Ohm
P=dbmtow(P avs)
Freq=RFfreq

OutBias

S1P _Eqn
S1
S[1,1]=LoadT uner
Z[1]=Z0

ClassDamp
X2

PARAMETER SWEEP

Set these values:

Var
E qn

vload

Output

VAR
ST IMULUS
P avs=23 _dBm
RFfreq=850 MHz
Vhigh=4.8
Vlow=-2.7

ParamSweep
Sweep1

Var
E qn

HARMONIC BALANCE
HarmonicBalance
HB1
Freq[1]=RFfreq
Order[1]=9

Statz_Model
FLC301XP
T rise=
Imelt=

Set Load and Source

impedances at
harmonic frequencies

Var
Eqn

Var VAR
Eqn
VAR
ImpedanceEquations
VAR3
Z_s_fund=10

VAR
VAR2
Z_l_2 =10*Z0 +j*0
Z_l_3 =10*Z0 +j*0
Z_l_4 =10* Z0 +j*0
Z_l_5 =10* Z0 +j*0
Z_s_2 =10* Z0 +j*0
Z_s_3 =10* Z0 +j*0
Z_s_4 =10* Z0 +j*0
Z_s_5 =10* Z0 +j*0

Refer to the example design file:

examples/RF_Board/LoadPull_prj/
HB1Tone_LoadPull_eqns for details
about how this simulation is run.
Refer to the data display file
"ReflectionCoefUtility" in the same
example project for help in setting
s11_rho and s11_center.

Narrow band input and output

matching and simulation results
I_Probe
Is_low

I_Probe
Is_high

Vs_low

1.5

Vs_high

L
L1
L=1 uH
R=

1.0

V_DC
SRC1
Vdc=Vhigh
I_Probe
Iload

InBias

vin

Input

OutBias
Output

L
L5
L=0.5 nH
R=

ClassDamp
X2

L
L3
L=1.2 nH
R=

C
C1
C=21 pF

vout

-0.5

R
R1
R=50 Ohm

-1.0
-1.5
0.0

Var
Eqn

OPTIONS

Var
Eqn

1.5

2.0

2.5

2.0

2.5

time, nsec
6

HarmonicBalance
HB1
Freq[1]=RFfreq
Order[1]=7

Statz_Model
FLC301XP
Trise=
Imelt=

VAR
STIMULUS1
fspacing=1 MHz
Max_IMD_order=7

N
Zin

Zin
Zin1
Zin1=zin(S11,PortZ1)

2
0
-2
-4
-6
0.0

10

ts(ID_FET2.i), A
ts(vds2), V

10

6
4
2
0
-2
1.0

1.5

time, nsec

2.0

2.5

0.5

1.0

1.5

time, nsec

6
4
2
0
-2

0.5

1.0

HARMONIC BALANCE

T ran
T ran1
StopTime=2 usec
MaxTimeStep=1 nsec

VAR
STIMULUS
P avs=14 _dBm
RFfreq=850 MHz
Vhigh=4.8
Vlow=-2.7

Options
Options1
Temp=25
Tnom=25
TopologyCheck=yes
V_RelTol=1e-6
V_AbsTol=1e-6 V
I_RelTol=1e-6
I_AbsT ol=1e-12 A
GiveAllWarnings=yes
MaxWarnings=10

0.0

0.5

TRANSIENT

Set these values:

ts(ID_FET1.i), A
ts(vds1), V

voad

0.0

ts(voad), V

P_nTone
PORT1
Num=1
Z=50 Ohm
Freq[1]=RFfreq
P[1]=dbmtow(Pavs)

L
L4
L=2.1 nH
R=

C
C2
C=2.1 pF

0.5

ts(vin), V

V_DC
SRC2
Vdc=Vlow

L
L2
L=1 uH
R=

0.0

0.5

1.0

1.5

time, nsec

2.0

2.5

Wide band matching using

coaxial
MSub
MSUB
MSub1
H=32 mil
Er=2.5
Mur=1
Cond=1.0E+50
Hu=3.9e+034 mil
T=1.4 mil
TanD=0
Rough=0 mil

Term
Term1
Num=1
Z=50 Ohm

MLIN
TL1
Subst="MSub1"
W=225.0 mil
L=675.0 mil

S-PARAMETERS
S_Param
SP1
Start=0.03 GHz
Stop=0.6 GHz
Step=50 MHz
C
C1
C=3.0 pF

C
C3
C=1.1 pF

Term
Term2
Num=2
Z=50 Ohm

C
C2
C=24 pF

N
Zin

Zin
Zin1
Zin1=zin(S11,PortZ1)

A conventional design allows the

coaxial transformer to transform the
impedance to obtain a match the
low end of the band, then add
additional low-pass matching
sections to lower the impedance at

freq
30.00MHz
80.00MHz
130.0MHz
180.0MHz
230.0MHz
280.0MHz
330.0MHz
380.0MHz
430.0MHz
480.0MHz
530.0MHz
580.0MHz
600.0MHz

Zin1
12.879 +j1.508
11.948 - j1.362
10.330 - j1.846
9.075 - j1.320
8.380 - j0.381
8.217 +j0.612
8.497 +j1.406
9.052 +j1.766
9.545 +j1.536
9.520 +j0.857
8.775 +j0.239
7.597 +j0.117
7.105 +j0.224

Using the MRF282S to simulate

narrow band VMCD @300MHz
One Tone Load P ull Simulation;
output power and P AE found at
each fundamental load impedance
I_P robe
Is_low

I_Probe
Is_high

Vs_low
V_DC
SRC2
Vdc=Vlow

L
L2
L=1 uH
R=

InBias

P_1Tone
PORT1
Num=1
Z=Z_s
P=dbmtow(P avs)
Freq=RFfreq

C
C1
C=1.0 uF

Set these values:

Var
E qn

VAR
ST IMULUS
Pavs=28 _dBm
RFfreq=300 MHz
Vhigh=20
Vlow=3

Input

L
L1
L=1 uH
R=

OutBias
Output

vout2

Vs_high
V_DC
SRC1
Vdc=Vhigh
C
C2
C=1.0 uF

Z0=50

I_Probe
Iload
vload
S1P _Eqn
S1
S[1,1]=LoadTuner
Z[1]=Z0

ClassDamp
X2

PARAMETER SWEEP
P aramSweep
Sweep1

Set Load and Source

impedances at
harmonic frequencies
Var
E qn

HARMONIC BALANCE
HarmonicBalance
HB1
Freq[1]=RFfreq
Order[1]=5

FSL_T ECH_INCLUDE
FSL_T ECH_INCLUDE
FTI

Specify desired F undamental Load Tuner coverage:

s11_rho is the radius of the circle of reflection coeffi cients
generated. However, the radius of the circle will be
reduced if it would otherwise go outside the Smith Chart.
s11_center is the center of the circle of generated reflection coeffi cients
pts is the total number of reflection coeffi cients generated
Z0 is the system reference impedance
s11_rho is the radius
Var VAR
and s11_center is the
E qn
SweepEquations
center of the circle.
s11_rho =0.7
(But this is just a
s11_center =-0.25 -j*0.03
static drawing.)
pts=100

Var
E qn
Meas
E qn

VAR
ImpedanceEquations

VAR
VAR2
Z_l_2 =10*Z0 +j*0
Z_l_3 =10*Z0 +j*0
Z_l_4 =10* Z0 +j*0
Z_l_5 =10* Z0 +j*0
Z_s_fund =10 +j*0
Z_s_2 =10* Z0 +j*0
Z_s_3 =10* Z0 +j*0
Z_s_4 =10* Z0 +j*0
Z_s_5 =10* Z0 +j*0

Refer to the example design file:

examples/RF_Board/LoadPull_prj/
HB1Tone_LoadPull_eqns for details
about how this simulation is run.
Refer to the data display file
"ReflectionCoefUtility" in the same
example project f or help in setting
s11_rho and s11_center.

Push_pull structure
FSL_MRF _ROOT_MODEL
MRF1
MODEL=MRF 282S

Sample
Class D
Amplifier

Input
Bias Port
Do not delete
this port.

I_Probe
ID_FET1

Output
Bias Port
Do not delete
this port.

Output
Port

vds1

1
T1

C
C3
C=1.0 uF

1
T2

Do not delete
this port.

Port
OutBias
Num=4

VD_FET1

Input
Port
Port
Input
Num=1

Port
InBias
Num=3

TF3
TF1
T1=1.00
T2=1.00

C
C4
C=1.0 uF

3
2

vds2

I_Probe
ID_F ET2

FSL_MRF _ROOT_MODEL
MRF2
MODEL=MRF 282S

TF 3
TF 2
T1=1.00
T2=1.00

vout1
SLC
SLC1
L=20.0 nH
C=14 pF

Port
Output
Num=2

Do not delete
this port.

Narrow band matching (input,

output)

Output
Bias Port

Input
Bias Port
I_Probe
Is_low

I_Probe
Is_high

FSL_MRF_ROOT_MODEL
MRF1
MODEL=MRF282S

Vs_high

Vs_low
L
L2
L=1 uH
R=

V_DC
SRC2
Vdc=Vlow

L
L1
L=1 uH
R=

I_Probe
ID_FET1

V_DC
SRC1
Vdc=Vhigh

VD_FET1

Input
Port
P_nTone
PORT1
Num=1
Z=50 Ohm
Freq[1]=RFfreq
P[1]=dbmtow(Pavs)

L
L4
L=6.4 nH
R=

C
C2
C=36 pF

I_Probe
Iload

vin

vds1

1
T1

C
C3
C=1.0 uF

vout1

TF3
TF1
T1=1.00
T2=1.00

Do not delete
this port.

1
T2

C
C4
C=1.0 uF

3
2

vds2

SLC
SLC1
L=20 nH
C=14 pF

vload
L
L5
L=4.8 nH
R=

TF3
TF2
T1=1.00
T2=1.00

OPTIONS
Options
Options1
Temp=25
Tnom=25
TopologyCheck=yes
V_RelTol=1e-6
V_AbsTol=1e-6 V
I_RelTol=1e-6
I_AbsTol=1e-12 A
GiveAllWarnings=yes
MaxWarnings=10

HARMONIC BALANCE
FSL_TECH_INCLUDE
Set these values:
Var
VAR
Eqn
STIMULUS
Pavs=28 _dBm
RFfreq=300 MHz
Vhigh=20
Vlow=5

I_Probe
ID_FET2

FSL_TECH_INCLUDE
FTI

N
Zin

Zin
Zin1
Zin1=zin(S11,PortZ1)

FSL_MRF_ROOT_MODEL
MRF2
MODEL=MRF282S

HarmonicBalance
HB1
Freq[1]=RFfreq
Order[1]=5

C
C1
C=30 pF

L
L3
L=8.7 nH
R=

vout

R
R1
R=50 Ohm

Narrow band simulation results

DC Power Calculations
The exists() function checks to be sure
the corresponding piece of data is in
the dataset. If it is not, then the
function returns 0.

Power Delivered and Power-Added

Efficiency Calculations
Eqn Pdel_Watts=real(0.5*vout[1]*conj(Iload.i[1]))
Pavs is the available source power, set on
the schematic, and passed into the dataset
using the Harmonic Balance controller.

Eqn Vs_l=exists("real(Vs_low[0])")
Eqn Vs_h=exists("real(Vs_high[0])")
Eqn Is_h=exists("real(Is_high.i[0])")

Eqn Pavs_Watts=10**((28-30)/10)
Eqn PAE=100*(Pdel_Watts-Pavs_Watts)/Pdc

Eqn Is_l=exists("real(Is_low.i[0])")

Eqn Pdel_dBm =10*log10(Pdel_Watts)+30

Eqn Pdc=Is_h*Vs_h +Is_l*Vs_l +1e-20

Pdel_Watts
36.194

40

30

20
1

10

0
-10

-1
0

time, nsec

45.112

Pdel_Watts/Pdc
0.802

50

40

30

20
1

10

0
-10

-1
0

time, nsec

ts(ID_ FET2.i), A

50

Pdc

ts(vds2), V

78.833

ts(ID_ FET1.i), A

ts(vds1), V

PAE

Final schematic
HARMONIC BALANCE

HAR MONIC BALANC E

MSub

Var
Eqn

HarmonicBalance
HB2
Freq[1]=0.3 GHz
Order[1]=3

VAR
VAR3
cs=0.01 uF
ls=19.5 nH
rs=15 Ohm

Var
Eqn

vd1
I_P robe
I_ds

v1
Var
Eqn

I_P robe
I_P robe1

VAR
VAR2
r1=5 Ohm
c1=2783 pF
c2=2 pF
ztin=16 Ohm
ztout=45 Ohm
ltin=1630 mil
ltout=2965 mil

FSL_MRF_ROOT_MODE L
MRF1
MODE L=MRF282S

C
C17
C=1.5 pF

Output
I_P robe
Iout

v2
I_P robe
I_P robe2

Reflect

FSL_MRF_ROOT_MODE L
MRF2
MODE L=MRF282S

Input
FSL_TECH_INCLUDE
FSL_TECH_INCLUDE
FTI

L
L11
L=1.4304 nH
R=

vgg

I_P robe
I_P robe4

vdd

I_P robe
I_P robe3
Meas
Eqn

L
L12
L=0.35 nH
R=

Final simulation results(1)

RFfreq
0.01000
0.03034
0.05069
0.07103
0.09138
0.11172
0.13207
0.15241
0.17276
0.19310
0.21345
0.23379
0.25414
0.27448
0.29483
0.31517
0.33552
0.35586
0.37621
0.39655
0.41690
0.43724
0.45759
0.47793
0.49828
0.51862
0.53897
0.55931

eta
3.18477
19.17149
26.69007
33.87357
38.05973
40.55221
52.89915
61.16288
63.58578
65.09090
69.37040
71.57224
74.12389
73.81647
71.28339
72.02632
76.89164
76.92763
75.85785
78.19259
80.02783
79.86804
79.41265
80.30537
82.43311
83.18813
81.66282
80.91020

Pdc
35.42361
45.42576
41.53192
53.37189
50.67507
47.00999
57.24243
62.92600
59.01689
54.75491
53.13651
50.51480
49.14442
48.24101
45.85446
44.49014
44.81067
45.92195
47.14371
48.25363
47.38484
47.11465
46.80491
45.77380
43.78908
41.57842
40.07803
39.06156

Pdel_Watts
1.12816
8.70879
11.08490
18.07896
19.28679
19.06359
30.28076
38.48735
37.52635
35.64047
36.86101
36.15457
36.42776
35.60981
32.68661
32.04461
34.45566
35.32667
35.76221
37.73077
37.92106
37.62955
37.16902
36.75882
36.09670
34.58831
32.72885
31.60478

PAE
-10.96363
8.13838
14.62255
24.48310
28.16952
29.89092
44.14363
53.19817
55.09351
55.93762
59.93833
61.65064
63.92564
63.42723
60.35343
60.76119
65.70708
66.01374
65.22680
67.80608
69.45087
69.23043
68.70464
69.35615
70.98762
71.13411
69.15753
68.07950

Gain
-6.47623
2.39960
3.44730
5.57170
5.85255
5.80199
7.81161
8.85313
8.74332
8.51940
8.66565
8.58163
8.61434
8.51572
8.14374
8.05760
8.37266
8.48109
8.53431
8.76702
8.78887
8.75535
8.70186
8.65366
8.57471
8.38932
8.14932
7.99753

Final simulation results(2)

60

2
1
0

20

-1
-2

ts(I_ds.i), A

ts(vd1), V

40

-3
-20

-4
0

time, nsec
eta
73.76255

Pdc
42.70324

Pdel_Watts
31.49900

PAE
62.02603

Gain
7.98301

The problem remain:

1. The Class D PA need a resonator tank to pull out the

2.
3.
4.

fundamental signal, to filter out the third time signal, so

I decide to divide the band into 3 parts, one from 30 to
88 MHz; 88MHz to 200MHz; 200MHz to 500MHz. We
can separate the signals by filter bank.
For the real device, the Rs isnt very small, so the
efficiency cant be so high. Because of the t ds , the Vds
and some overlap with Ids, it also kill some efficiency.
To achieve better performance at low frequency band, I
have to increase the Vgg.
ADS is very hard to converge when simulation.

Thank you!!!