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Unit III -RTL Synthesis

Coding guideline for synthesis.


Logic Inference: Order dependence.
Optimization and mapping constraints
(clock, delay, area, design).
An overview of the synthesis based
ASIC design flow.
Synthesis Environment. technology
library: technology libraries, logic
library basics, delay calculations

An ASIC/VLSI Design Flow

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

An RTL Synthesis Flow

12-6

A Physical Synthesis Flow

12-7

Logic Synthesis
assign z=a&b

a
z
b

What is Synthesis
synthesis
/sinth siss/
noun (pl. syntheses /sinth seez/) 1 the
combination of components to form a connected
whole. Often contrasted with ANALYSIS. 2 the
production of chemical compounds by reaction
from simpler materials.
DERIVATIVES synthesist noun.
ORIGIN Greek sunthesis, from suntithemai
place together.

Synthesis
Translation from a higher-level description
to a lower-level description
Logic or RTL synthesis: Translation of RTL
code to logic gates and other basic
components

Synthesis
Combining pre-existing elements to form
something new

Logic Synthesis
Combining primitive logic functions to form a
design netlist that meets functional and
design goals
Functional Description (HDL)
Goals
TP
TP

Netlist
TP
TP

TP=Technology Primitive

Why Synthesis?
HDL
10k
residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] =
16h0000;

Gate
1M

Transistor
5M

# of Elements
Complexity

D
Z

Polygon
100M

Effort
Time
Cost
Layout
5

Logic Synthesis
Logic Synthesis = Translation + Mapping + Optimization
residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] =
16h0000;

Translation
(read)
Mapping/Optimization
(compile)

Hardware Description
Language (HDL)

Generic Boolean
(GTECH)

Target Technology
(standard cells)

Functional Description

Written in Hardware Description Language (HDL)


Verilog/VHDL
Register Transfer Level (RTL)
Synchronous => reliable behavior

Simplifies timing verification


Simplifies optimization algorithms
Optimal results

Coding style affects results

Translation

residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] =
16h0000;

Hardware Description
Language (HDL)

Converts HDL to functional


boolean equivalent
HDL syntax/rule checks

Translation
(read)

Optimizes HDL
Arithmetic function mapping
Sequential function mapping

Combinational function mapping

Generic Boolean
(GTECH)

Mapping/Optimization

Maps Boolean functions to


technology specific primitive
functions
Modifies mapping to meet design
goals

Design Rules

Timing
Area
Power

Generic Boolean
(GTECH)

Mapping/
Optimizatio
n
(compile)

Target Technology
(standard cells)

RTL Design Flow


HDL
manual
design

RTL
Synthesis

Library/
module
generators

netlist

physical
design
layout

logic
optimization
netlist

clk

clk

Logic optimization flow


LOGIC EQUATIONS
TECHNOLOGY-INDEPENDENT
OPTIMIZATION
TECH-DEPENDENT OPTIMIZATION
(MAPPING, TIMING)
OPTIMIZED LOGIC NETWORK

Factoring
Commonality Extraction
LIBRARY

Logic optimization flow


LOGIC EQUATIONS
TECHNOLOGY-INDEPENDENT
OPTIMIZATION
TECH-DEPENDENT OPTIMIZATION
(MAPPING, TIMING)
OPTIMIZED LOGIC NETWORK

Factoring
Commonality Extraction
LIBRARY

Why logic optimization?


Transistor count redution
AREA
Circuit count redution
POWER
Gate count (fanout) reduction DELAY
(Speed)
Area reduction, power reduction and delay
reduction improves design

Boolean Optimizations

Involves:
Finding common subexpressions.
Substituting one expression into another.
Factoring single functions.

f1 = AB + AC + AD + AE + A BC D E

F =
f2 = AB + AC + AD + AF + A BC D F

Find common
expressions
f = A( B + C + D + E ) + A BC DE

1
F =
f2 = A( B + C + D + F ) + A BC DF

Extract
B + Csubstitute
+ D
common expression
g = and
G f1

f2

= A ( g1 + E ) + A E g1

= A ( g1 + F ) + A F g1

Algebraic Optimizations

Algebraic techniques view equations as


polynomials
Rules of polynomial algebra are used
For e.g. in algebraic substitution (or
division) if a function f=f(a,b,c) is
divided by g=g(a,b), a and b will not
appear in f/g
Boolean algebra rules are not applied

Logic optimization flow


LOGIC EQUATIONS
TECHNOLOGY-INDEPENDENT
OPTIMIZATION
TECH-DEPENDENT OPTIMIZATION
(MAPPING, TIMING)
OPTIMIZED LOGIC NETWORK

Factoring
Commonality Extraction
LIBRARY

Optimization: Constraint-Driven
create_clock period 10 name CLK [get_port clock_in]
set_input_delay 4 -clock CLK [get_ports data_in*]
Large
set_output_delay 3.5set_output_delay
-clock CLK [get_ports
3.5 -clock CLK [get_ports data_out*]
set_max_area 0

Area

Small
Short

Delay

Long

Design goals (constraints) drive optimization

10

Static Timing Analysis


TOP
A

D Q

QB

QB

FF2

D Q

Z
FF3

CLK

STA breaks designs into sets of signal paths


Each path has a startpoint and an endpoint:

Startpoints:
Input ports
Clock pins of Flip-Flops or registers

Endpoints
: ports
Output
All input pins of sequential devices (except clock pins)

11

Optimization: Slack-Driven
FF1
FF2

Q
U2
F1

Clk

CLK

FF1/clk

F1

U3

CLK

1.1ns

Data
Arrival
Data
Require
d

5.1ns

FF2/D
Setup

FF2/clk
1ns

5ns

11

12

Synthesis/Physical Synthesis
RTL
Timing Constraints
Floorplan
Timing/Logic Library
IP Library(DW)
Physical Library
Synthesis
HDL Translation

residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] =
16h0000;

Hardware Description
Language (HDL)

Synthesis
(DC, DCT)

Static Timing (DC/DCT/PC/PT)


Formal Equivalence (FM) Power
Analysis (DC/DCT/PC/PT-PX)

Mapping
Static Timing
Placement

Meets
Spec?

Routing Estimation
Optimization

No

Design Rule Fixing


Scan-Ready Netlist

Yes

Target Technology
(standard cells)

DFT

DC=Design Compiler DCT=DC Topographical PC=Physical Compiler PT=PrimeTime FM=Formality PT-PX=PrimeTime-PX DW=DesignWare

13

RTL synthesis

SYNTHESIS

Partitioning for Synthesis

Guideline
Avoid internally generated clocks
D

SET

CLR

SET

CLR

Instead, use a separate block for clock


generation

Rule
Avoid combinational feedback
CLK

SET

CLR

COMB

COMB

COMB

SET

CLR

Do not use if statements to describe


larger than 2-to-1 MUXs
if sel = 00 then

sel

o <= a;
elsif sel = 01 then
o <= b;
elsif sel = 10 then
o <= c;
else
o <= d;
end if;

10
d
01
c
b

00
o

Use Case statement instead


sel

case sel is
when 00 =>
o <= a;
when 01 =>
o <= b;

c
o

when 10 =>
o <= c;

when others =>


o <= d;
end case;

Register all outputs


Bad

CLK

SET

CLR

Better

CLK

SET

CLR

COMB

COMB

COMB

SET

CLR

COMB

COMB

COMB

SET

CLR

Ideal
CLK

SET

CLR

COMB

COMB

COMB

SET

CLR

Avoid glue logic at the top


TOP

Incorrect

COMB

SET

COMB

SET

CLK
CLR

Correct

CLR

TOP

COMB

SET

COMB

SET

CLK
CLR

CLR

RTL coding for synthesis


Keep code technology independent (no
instantiations of technology primitives)
Clock gating logic and reset generation kept
in one block
Avoid multiple clocks per block (Sync logic
should be in a separate module)
No glue logic at the top
Register all outputs

RTL coding for logic


No incomplete sensitivity lists
Use the case statement for muxes,
specifying the others case

RTL coding for state machines


Use enumerated types, do not perform state
assignment
Separate combinational logic from state
registers
Use case statements

Specifying design constraints


Timing (clock frequency, I/O timing)
Area (mm^2, #CLBs)
I/O pads and pins

Guideline
Avoid mixed clock edges
D

SET

COMB

SET

CLK
CLR

CLR

If not possible, isolate mixed clock domains


D

SET

COMB

SET

CLK
CLR

CLR

Guideline 1:- Declare every possible state


in conditional statements. Missing a
declaration can result in un-intentional
latches in design.

Guideline 2:- All the signals coming


to/from external world should be properly
registered to avoid setup time violations.

Guideline 3:- All the IOs should be


properly constrained during synthesis and
layout to avoid setup or hold time
violations.

Guideline 4:- Implementing clock domain


crossing is the most complicated design
scenario in digital circuits. Necessary steps
to design involves detailed analysis of the
clocks across the domain.
Following are some ideas to implement
clock domain crossing:
Use rate change FIFO, Double clocking,
Gray encoders for counters.

Guideline 5:- Wires and Registers should be correctly


implemented in Verilog. Registers must be used
within always blocks. Wires are used for connectivity
outside always blocks and are generally used with
assign statements or for connectivity not requiring
any registered delay.
Guideline 6: Blocking vs. non-blocking stms.
Blocking statements are always used within
combinatory block to execute statements in a
sequence. Non blocking statements are always
executed in a sequential logic block to execute all
statements in at either clock edge.

Guideline 7: Never mix blocking and nonblocking stms in a single always block in Verilog.
Guideline 8:- Suggested approach to write
synthesizable RTL is to separate the synchronous
and combinational logic into separate processes
(always blocks in Verilog).
Guideline 9:- After simulating the design, always
synthesize it and check for latches, unbounded
component, tri-state logic etc.
Guideline 10: - Conditional IF statements should
not be used in parallel states. Case statements best

Chapter 12: Synthesis

The Architecture of Synthesizer

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-14

Chapter 12: Synthesis

Logic Synthesis (Logic Optimization)


Major concerns
functional metric: fanin, fanout, and others
non-functional metric: area, power, and delay

Two phases of logic synthesis


technology-independent
technology-dependent

Library binding

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-17

Chapter 12: Synthesis

Technology-Independent Logic Optimization


Technology-independent logic synthesis
Simplification
Restructuring network
Restructuring delay

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-18

Chapter 12: Synthesis

Technology Mapping
A two-step approach
FlowMap method

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-20

Chapter 12: Synthesis

A Two-Step Approach

Decompose the network


Reduce the number of nodes

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-21

Chapter 12: Synthesis

FlowMap Method
Break the network into LUT-sized blocks
Reduce the number of logic elements (LUTs)

Three LUTs are required

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-22

Chapter 12: Synthesis

Coding guidelines

Coding Guidelines for Synthesis


Guidelines for Clocks
Guidelines for Resets
Partitioning for Synthesis

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-42

Chapter 12: Synthesis

Coding Guidelines for Synthesis


Goals of coding guidelines

Testability
Performance
Simplification of static timing analysis
Matching gate-level behavior with that of the original
RTL codes

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-43

Chapter 12: Synthesis

Guidelines for Clocks


Using single global clock
Avoiding using gated clocks

Avoiding mixed use of both positive and negative


edge-triggered flip-flops
Avoiding using internally generated clock signals

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-45

Chapter 12: Synthesis

Guidelines for Clocks

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-46

Chapter 12: Synthesis

Guidelines for Resets


The basic design issues of resets are
Asynchronous or synchronous?
An internal or external power-on reset?
More than one reset, hard vs. soft reset?

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-48

Chapter 12: Synthesis

Guidelines for Resets


The basic writing styles:
always @(posedge clk or posedge reset)
if
(reset) ..
else ..
Asynchronous reset

The reset signal should


flops

always @(posedge clk)


if
(reset) ..
else ..
Synchronous reset

be a direct clear
of all flip-

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-49

Chapter 12: Synthesis

Guidelines for Resets


Asynchronous reset
Hard to implement
Does not require a free-running clock
Does not affect flip flop data timing
Makes STA more difficult

Makes the automatic insertion of test structure more


difficult

Synchronous reset
easy to implement
Requires a free-running clock
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-50

Chapter 12: Synthesis

Guidelines for Resets


Avoid internally generated conditional resets
always @(posedge gate or negedge reset_n or posedge timer_load_clear)
if (!reset_n || timer_load_clear) timer_load <= 1b0;
else timer_load <= 1b1;

When a conditional reset is required:


assign timer_load_reset = !reset_n || timer_load_clear;
always @(posedge gate or posedge timer_load_reset)
if (timer_load_reset) timer_load <= 1b0;
else timer_load <= 1b1;

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-51

Chapter 12: Synthesis

Partitioning for Synthesis


Keep related logic within the same module

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-53

Chapter 12: Synthesis

Partitioning for Synthesis


Register all outputs

Separating structural logic from random logic

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-54

Chapter 12: Synthesis

Partitioning for Synthesis


Maintaining the original hierarchy

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

12-55

Synthesis Shortcomings
Design partitioning
A difficult problem requiring much user interaction

Circuit timing estimates


High-level synthesis tools use pre-layout estimates
- not accurate for large (e.g. >6000 gates) circuits

May be difficult to associate resulting design


with original description

Propagation delay
Delay: time required to propagate a
signal from an input port to an output
port
Cell level delay: most accurate
Simplified model:

Gate delay Parasitic effect

The impact of wire becomes more


dominant as devices get smaller

Propagation delay

Cload C gi Cwi
i

System delay

The longest path (critical path) in the


system
The worst input to output delay

False path may exists:

Synthesis with timing


constraint

Multi-level synthesis is flexible


It is possible to reduce by delay by adding
extra logic
Synthesis with timing constraint
1.
2.
3.

Obtain the minimal-area implementation


Identify the critical path
Reduce the delay by adding extra logic

Area-delay trade-off curve

Timing Hazards
Propagation delay: time to obtain a
stable output
Hazards: the fluctuation occurring
during the transient period
Static hazard: glitch when the signal
should be stable
Dynamic hazard: a glitch in transition

Due to the multiple converging paths


of an output port

Timing Hazards
Static-hazard
consider
sh=ab+bc;
for a=c=1

Timing Hazards
Dynamic hazard
consider
changing b for
(a=c=d=1)

Dealing with hazards


Some hazards can be eliminated in
theory

Delay sensitive design and


its danger
Boolean algebra
the theoretical model for digital design and
most algorithms used in synthesis process
algebra deals with the stabilized signals

Delay-sensitive design
Depend on the transient property (and
delay) of the circuit
Difficult to design and analyze

Delay sensitive design and


its danger
Whats can go wrong:
E.g., pulse <= a and (not a);
During logic synthesis, the logic expressions will be
rearranged and optimized.
During technology mapping, generic gates will be remapped
During placement & routing, wire delays may change
It is bad for testing verification

If delay-sensitive design is really needed, it


should be done manually, not by synthesis

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