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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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12-7
Logic Synthesis
assign z=a&b
a
z
b
What is Synthesis
synthesis
/sinth siss/
noun (pl. syntheses /sinth seez/) 1 the
combination of components to form a connected
whole. Often contrasted with ANALYSIS. 2 the
production of chemical compounds by reaction
from simpler materials.
DERIVATIVES synthesist noun.
ORIGIN Greek sunthesis, from suntithemai
place together.
Synthesis
Translation from a higher-level description
to a lower-level description
Logic or RTL synthesis: Translation of RTL
code to logic gates and other basic
components
Synthesis
Combining pre-existing elements to form
something new
Logic Synthesis
Combining primitive logic functions to form a
design netlist that meets functional and
design goals
Functional Description (HDL)
Goals
TP
TP
Netlist
TP
TP
TP=Technology Primitive
Why Synthesis?
HDL
10k
residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] =
16h0000;
Gate
1M
Transistor
5M
# of Elements
Complexity
D
Z
Polygon
100M
Effort
Time
Cost
Layout
5
Logic Synthesis
Logic Synthesis = Translation + Mapping + Optimization
residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] =
16h0000;
Translation
(read)
Mapping/Optimization
(compile)
Hardware Description
Language (HDL)
Generic Boolean
(GTECH)
Target Technology
(standard cells)
Functional Description
Translation
residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] =
16h0000;
Hardware Description
Language (HDL)
Translation
(read)
Optimizes HDL
Arithmetic function mapping
Sequential function mapping
Generic Boolean
(GTECH)
Mapping/Optimization
Design Rules
Timing
Area
Power
Generic Boolean
(GTECH)
Mapping/
Optimizatio
n
(compile)
Target Technology
(standard cells)
RTL
Synthesis
Library/
module
generators
netlist
physical
design
layout
logic
optimization
netlist
clk
clk
Factoring
Commonality Extraction
LIBRARY
Factoring
Commonality Extraction
LIBRARY
Boolean Optimizations
Involves:
Finding common subexpressions.
Substituting one expression into another.
Factoring single functions.
f1 = AB + AC + AD + AE + A BC D E
F =
f2 = AB + AC + AD + AF + A BC D F
Find common
expressions
f = A( B + C + D + E ) + A BC DE
1
F =
f2 = A( B + C + D + F ) + A BC DF
Extract
B + Csubstitute
+ D
common expression
g = and
G f1
f2
= A ( g1 + E ) + A E g1
= A ( g1 + F ) + A F g1
Algebraic Optimizations
Factoring
Commonality Extraction
LIBRARY
Optimization: Constraint-Driven
create_clock period 10 name CLK [get_port clock_in]
set_input_delay 4 -clock CLK [get_ports data_in*]
Large
set_output_delay 3.5set_output_delay
-clock CLK [get_ports
3.5 -clock CLK [get_ports data_out*]
set_max_area 0
Area
Small
Short
Delay
Long
10
D Q
QB
QB
FF2
D Q
Z
FF3
CLK
Startpoints:
Input ports
Clock pins of Flip-Flops or registers
Endpoints
: ports
Output
All input pins of sequential devices (except clock pins)
11
Optimization: Slack-Driven
FF1
FF2
Q
U2
F1
Clk
CLK
FF1/clk
F1
U3
CLK
1.1ns
Data
Arrival
Data
Require
d
5.1ns
FF2/D
Setup
FF2/clk
1ns
5ns
11
12
Synthesis/Physical Synthesis
RTL
Timing Constraints
Floorplan
Timing/Logic Library
IP Library(DW)
Physical Library
Synthesis
HDL Translation
residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] =
16h0000;
Hardware Description
Language (HDL)
Synthesis
(DC, DCT)
Mapping
Static Timing
Placement
Meets
Spec?
Routing Estimation
Optimization
No
Yes
Target Technology
(standard cells)
DFT
DC=Design Compiler DCT=DC Topographical PC=Physical Compiler PT=PrimeTime FM=Formality PT-PX=PrimeTime-PX DW=DesignWare
13
RTL synthesis
SYNTHESIS
Guideline
Avoid internally generated clocks
D
SET
CLR
SET
CLR
Rule
Avoid combinational feedback
CLK
SET
CLR
COMB
COMB
COMB
SET
CLR
sel
o <= a;
elsif sel = 01 then
o <= b;
elsif sel = 10 then
o <= c;
else
o <= d;
end if;
10
d
01
c
b
00
o
case sel is
when 00 =>
o <= a;
when 01 =>
o <= b;
c
o
when 10 =>
o <= c;
CLK
SET
CLR
Better
CLK
SET
CLR
COMB
COMB
COMB
SET
CLR
COMB
COMB
COMB
SET
CLR
Ideal
CLK
SET
CLR
COMB
COMB
COMB
SET
CLR
Incorrect
COMB
SET
COMB
SET
CLK
CLR
Correct
CLR
TOP
COMB
SET
COMB
SET
CLK
CLR
CLR
Guideline
Avoid mixed clock edges
D
SET
COMB
SET
CLK
CLR
CLR
SET
COMB
SET
CLK
CLR
CLR
Guideline 7: Never mix blocking and nonblocking stms in a single always block in Verilog.
Guideline 8:- Suggested approach to write
synthesizable RTL is to separate the synchronous
and combinational logic into separate processes
(always blocks in Verilog).
Guideline 9:- After simulating the design, always
synthesize it and check for latches, unbounded
component, tri-state logic etc.
Guideline 10: - Conditional IF statements should
not be used in parallel states. Case statements best
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Library binding
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Technology Mapping
A two-step approach
FlowMap method
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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A Two-Step Approach
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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FlowMap Method
Break the network into LUT-sized blocks
Reduce the number of logic elements (LUTs)
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Coding guidelines
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Testability
Performance
Simplification of static timing analysis
Matching gate-level behavior with that of the original
RTL codes
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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be a direct clear
of all flip-
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Synchronous reset
easy to implement
Requires a free-running clock
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Synthesis Shortcomings
Design partitioning
A difficult problem requiring much user interaction
Propagation delay
Delay: time required to propagate a
signal from an input port to an output
port
Cell level delay: most accurate
Simplified model:
Propagation delay
Cload C gi Cwi
i
System delay
Timing Hazards
Propagation delay: time to obtain a
stable output
Hazards: the fluctuation occurring
during the transient period
Static hazard: glitch when the signal
should be stable
Dynamic hazard: a glitch in transition
Timing Hazards
Static-hazard
consider
sh=ab+bc;
for a=c=1
Timing Hazards
Dynamic hazard
consider
changing b for
(a=c=d=1)
Delay-sensitive design
Depend on the transient property (and
delay) of the circuit
Difficult to design and analyze