Initially (at t0), the counters FFs are all LOW.

Since this is not the terminal state for the

counter, output RCO will be LOW also.
The first PGT on the CLK input occurs at t1
and, since all control inputs are HIGH, the
counter will increment to 0001.
The counter continues to count up with each
PGT until t2.
The input is LOW for t2. This will
synchronously reset the counter to 0000 at t2.
After t2, the CLR input goes inactive (HIGH) so
the counter willstart counting up again from
0000 with each subsequent PGT.
The LOAD input is LOW for t3. This will
synchronously load the applied data value
1100 (12) into the counter at t3.
After t3, the LOAD input goes inactive (HIGH),
so the counter will continue counting up from
1100 with each subsequent PGT until t4.
The counter output does not change at t4 or
t5, since either ENP or ENT (the count enable
inputs) is LOW. This holds the count at 1110
(14).
At t6, the counter is enabled again and counts
up to 1111 (15), its terminal state.
As a result, the RCO output now goes HIGH. At
t7, another PGT on CLK will make the counter
recycle to 0000 and RCO returns to a LOW
output.

 Initially (at t0) the counters FFs are all LOW. Since
this is not the terminal state for the BCD counter,
output RCO will be LOW also.
The first PGT on the CLK input occurs at t1 and,
since all control inputs are HIGH, the counter will
increment to 0001.
The counter continues to count up with each PGT
until t2.
The asynchronous CLR input goes LOW at t2 and
will immediately reset the counter to 0000 at that
point.
At t3, the CLR input is still active (LOW), so the
PGT of the CLK input will be ignored and the
counter will stay at 0000.
Later the CLR input goes inactive again and the
counter will count up to 0001 and then to 0010.
At t4, the count enable ENP is LOW, so the count
holds at 0010.
For subsequent PGTs of the CLK input, the counter
is enabled and counts up until t5.
The LOAD input is LOW for t5. This will
synchronously load the applied data value 0111 (7)
into the counter at t5.
At t6, the count enable ENT is LOW, so the count
holds at 0111. For the two subsequent PGTs after
t6, the counter will continue counting up since it is
re-enabled.
At t7, the BCD
counter reaches its terminal state 1001 (9) and the
RCO output now goes HIGH.
At t8, ENP is LOW and the counter stops counting
(remaining at 1001).
At t9, while ENT is LOW, the RCO output will be

 Both chips are up/down counters and have an

asynchronous, active-LOW load input.
This means that as soon as LOAD goes LOW, the
counter will be preset to the parallel data on the D,
C, B, A (A is LSB and D is MSB) input pins.
If the load function is inactive, it does not matter
what is applied to the data input pins.
The load input has priority over the counting
function.
To count, the LOAD control input must be inactive
(HIGH) and the
count enable control must be LOW.
The count direction is controlled by the D/U control
input.
If D/Uis LOW, the count is incremented with each
PGT on CLK, while a HIGH on will decrement the
count.
Both counters automatically recycle in either count
direction. The decade counter recycles to 0000 after
state 1001 (9) when counting up or to 1001 after
state 0000 when counting down.
The binary counter will recycle to 0000 after 1111
(15) when counting up or to 1111 after state 0000

 MAX/MIN is an active-HIGH output that detects

(decodes) the terminal state of the counter.
Since they are up/down counters, the terminal
state depends on
the direction of the count. The terminal state
(MIN) for either counter when counting down
is 0000 (0).
However when counting up, the terminal state
(MAX) for a decade counter is 1001 (9), while
the terminal state for a MOD-16 counter is
1111 (15). Note that MAX/MIN detects only
one state in the count sequenceit just
depends on whether it is counting up or down.
The active- LOW RCO output also detects the
appropriate terminal state for the counter,
but it is a bit more complicated. First, it is only
enabled when CTEN is LOW.
Additionally, RCO will only be LOW while the
CLK input is also LOW. So essentially will
mimic the CLK waveform only during the
terminal state
while the counter is enabled.

Refer to Figure 7-17, where a 74HC190 has the input

signals given in the timing diagram applied. The
parallel data inputs are permanently connected as
0111. Assume the counter is initially in the 0000 state,
and determine the counter output waveforms.

 Initially (at t0), the counters FFs are all LOW.

Since the counter is enabled (CTEN=0) and
the count direction D/U=0 control the BCD
counter will start counting up on the first PGT
applied to CLK at t1 and continues to count up
with each PGT until t2, where the count has
reached 0101.
The asynchronous LOAD input goes LOW at t2
and will immediately load 0111 into the
counter at that point.
At t3, the LOAD input is still active (LOW), so
the PGT of the CLK input will be ignored and
the counter will stay at 0111.
Later the LOAD input goes HIGH again and
the counter will count up to 1000 at the next
PGT.
At t4, the counter increments to 1001, which
is the terminal state for a BCD up counter and
the MAX/MIN output goes HIGH.
During t5, the counter is at its terminal state
and the CLK input is LOW, so goes RCO LOW.
For subsequent PGTs of the CLK input, the
counter recycles to 0000 and continues to
count up until t6.
Just prior to t6, the D/U control changes to a
HIGH.
This will make the counter count down at t6
and again at t7, where it will be at state 0000,
which now is the terminal state since we are
counting down, and MAX/MIN will output a
HIGH.
During t8, when the CLK input RCO goes