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Agenda
Why Verification?
Verification Alternatives
Languages for System Modeling and Verification
Concluding Remarks
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Why Verification
Goal of verification:
Importance of Verification
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Kluwer Acade
Reconvergence Model:
Transformation
Initial
Specification
Transformation
Result
Transformation
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The Idea:
RTL Coding
Written
Specification
RTL Code
Verification
How it works
RTL Coding
Written
Specification
Interpretation
RTL Code
Verification
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Now
Code
Code
P&R
Synthesis
P&R
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mor
hese re-spins.
With increasing chip complexity, this situation could
worsen.
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Cost of
Fixing
a Problem
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Behaviora
l
Design
RTL
Design
Gate
Level
Design
Device
Production
11
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Module Instance:
Device
Under
Verification
(DUV)
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Comparing approaches
Visual inspection
Output comparison
Output checking
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Stimulus
Generator
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Device
under
Verification
(DUV)
Waveform Viewer
OR
Text Output
15
Testbench Approaches
Output Comparison
Testbench File
Gold
Vectors
Reference
Model
Output
Comparator
Stimulus
Generator
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Device
under
Verification
(DUV)
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Error/Status
Messages
Testbench Approaches
Self-Checking
Testbench File
Input Signals
Output
Signals
Stimulus
Generator
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Device
under
Verification
(DUV)
Error/Status
Messages
Output
Checker
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Self-checking testbenches
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Emotionally or Intuitively;
Out of money? Exhausted?
Competing product is there.
Software people are happy with your hardware.
There have been no bugs reported for two weeks.
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Agenda
Why Verification ?
Verification Alternatives
Simulation
Emulation
Prototyping
Formal verification
Semi-Formal verification
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20
er
F a st
duct
o
r
p
inal
f
o
t
Prototyping
oser
l
c
,
d
e
e
sp
Hardware
Accelerated
Simulation
Emulation
Simulation
Basic
verification
tool
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Semi-formal
Verification
Bigg
e
r cov
erag
e
Formal
Verification
21
Software Simulation
Other parts
are not even
tested.
DUV
a = 1;
Some part of
the design is
tested
repeatedly.
#20 b = 1;
$display (status is = %d,c);
...
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Cycle-Based Simulation
Combinational
logic
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Combinational
Combinational
logic
logic
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Event-driven
Timing resolution
Clock cycle
User-defined minimum
delay
Evaluation time
point
Evaluation node
Every flip-flop
boundary
Simulation time
Proportional to
the (number of
cycles) times
(C/L size *
number of F/Fs)
Proportional to the
number of events
(circuit size* no. of
cycles*event density)
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Software Simulation
Pros
The design size is limited only by the computing re
source.
Simulation can be started as soon as the RTL descri
ption is finished.
Set-up cost is minimal.
Cons
Slow (~100 cycles/sec) ; Speed gap between
the speed of software simulation and real
silicon widens. (Simulation speed = size of
the circuit simulated / speed of the simulation
engine)
The designer does not exactly know how
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much percentage of the design have been
Emulation
Prototyping
Simulation
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Hardware
Accelerated
Simulation
Emulation
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Emulation
Logic design
Design
mapping
&
>
&
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External pins
27
Prototyping
Pros
Higher (than emulation) clock rate (over 1M cycles
/sec) due to specific design of prototyping board.
Components as well as the wiring can be customiz
ed for the corresponding application.
Can be carried along. (Hardware Emulation? Forge
t it!)
Cons
Not flexible for design change
(Every new prototype requires a new board archite
cture. / Even a small change requires a new PCB.)
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Formal verification
Application of logical reasoning to the development of digita
l system
Both design and its specification are described by a language
in which semantics are based on mathematical rigor.
Semi-formal verification
Combination of simulation and formal verification.
Formal verification cannot fully cover large designs, and simu
lation can come to aid in verifying the large design.
Simulation
Semi-formal
Verification
Formal
Verification
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Formal Verification
Objective
Pros
Cons
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Refined
Refined
Model
Model
Cons
Memory explosion
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PCI
PCIDMA
DMAController
Controller
PCI
devsel
assertion is
violated!
event devsel :
if (FRAME=0) [1..4]
(DEVSEL=0)
assert(devsel);
Report to the
user!!
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Formal verification
Setup
testbench
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Describe
assertions
Efficiency of
assertion
Simulation
Time, Effort
By IBM in Computer-Aided Verification 2000
34
Coverage-directed verification
Increase the probability of bug detection by checking the qual
ity of stimulus
Used as a guide for the generation of input stimulus
Test
TestPlan
Plan
(Coverage
(Coverage
Definition)
Definition)
Directives
Directives
Coverage
Coverage
Reports
Reports
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Random
Random
Test
Test
Generator
Generator
Coverage
Coverage
analysis
analysis
Test
TestVectors
Vectors
Simulation
Simulation
35
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Semi-Formal Verification
Pros
Cons
Challenges
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Speed Comparison
Speed (Cycles/sec, log scale)
10MHz
1~10MHz
500KHz
1MHz
100kHz
100 kHz
10 kHz
50-70Hz
100Hz
0 kHz
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Software HardwareHardware
Simulation Accelerated
emulation
Simulation
(from Quickturn
(from
presentation)
Quickturn/Dynalith
Presentation)
Prototyping
39
Semi-formal
(Assertionbased
verification)
Design Complexity
Gate counts
Comments
Simulation/Semiformal verification
Unlimited
Emulation/Hardwar
e-accelerated
simulation
1M~16M gates
Depends on the
number of FPGAs in
the architecture
Prototyping
1M~5M gates
Depends on the
components on the
board
Formal verification
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Semi-formal
Emulation
/Accelerated simulation
Prototyping
Simulation
Redirection
of
testbench
constraints
Simulatio
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n setup
Semi-formalEmulation
setup
setup
Prototypin
g setup
Verification Time
41
Agenda
Why Verification ?
Verification Alternatives
Languages for System Modeling and Verification
Concluding Remarks
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42
Language for
Software development
Assembly
Language for
Hardware test
C++
C
SystemC
TestBuilder
Vera
Language for
Hardware description
Schematic
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Past
SystemVerilog
Verilog
VHDL
present
43
Future
Pros
C/C++
HDL
(Verilog,
VHDL)
Familiarity
SystemC
Easily
SystemVerilo
g
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Easy
to describe H/W
designs
connected to
C/C++ codes.
Easy to model system
behaviors.
Easy
Cons
Unable
to handle some
hardware
environments.
Focuses
tools
(simulation, synthesis,
etc.)
Few
tools (simulation,
synthesis, etc.)
Subset support
44
Ideal Verification
10MHz
Solution
1MHz
100KHz
Make it cheaper
Make it faster
Real Silicon
Rapid Prototype
HW Emulator
10KHz
1KHz
100Hz
10Hz
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HW Accelerator
SW Simulator
Investment
45
RTL Description
(Verilog HDL)
Synthesis
Gate Level
Simulation
Hardware
Emulation
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Verification Completed
RTL Simulation
For version
control
46
Concurrent Verification
Without Emulation
SW
HW
Sequential
Verification
Design
Design
CHIP
System
Integration
Code
Hardware
Integration
Build
Design
Fab
Debug
Debug
Back
annotation
With Emulation
SW
HW
Design
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Concurrent
Verification
Code
Design
Build
CHIP
HW emulation
Time
Design
Chip
Debug
Fab
HW integration
& HW Debug
Sys integration
& SW Debug
Final
Integration
Back annotation
Early to
Market!!
Debug
47
Debug
Agenda
Why Verification ?
Verification Alternatives
Languages for System Modeling and Verification
Concluding Remarks
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48
Concluding Remarks
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Concluding Remarks
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Thank You!!
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Questions ???
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Appendices
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53
design.
Internal node probing Top block
enables this by
wiring-out the internal Sub-block
nodes to the boundary
of the DUT top block.
DUT
Built-In
Logic
Analyzer
Internal node
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External
Dump
Memory
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Trigger
Logic Equation Module
History Register
Transaction Register
Random Generator
Traffic Analyzer
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Application
FPGA prototyping
HW/SW co-verification
Silicon validation
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from SimPOD
CPU
C Language
Instruction
Behavior
In C
(Polaris)
Virtual Chip
HDL
Microarchitecture
in C
FlexPC
RT-Level
in Verilog
Gate-Level
in Verilog
Using
MCV
PLI
Real
Mother-board
H/W
Peripherals
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Virtual PC in C language
(VPC)
Prototyping
Prototyping
Simulation
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Hardware
Accelerated
Simulation
Emulation
59
A Prototyping Example
Switch board
Prototype of 4-Port G
igabit Ethernet Switc
h
MPC860
microprocessor
Processor board
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