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Introduction to

CMOS VLSI
Design

MOS Behavior in DSM

Outline
Transistor I-V Review
Nonideal Transistor Behavior
Velocity Saturation
Channel Length Modulation
Body Effect
Leakage
Temperature Sensitivity
Process and Environmental Variations
Process Corners

CMOS VLSI Design

MOS Behavior inSlide


DSM2

Ideal Transistor I-V


Shockley 1st order transistor models

Vgs Vt

V
I ds Vgs Vt ds Vds Vds Vdsat
2

Vgs Vt
Vds Vdsat

2
CMOS VLSI Design

cutoff
linear
saturation

MOS Behavior inSlide


DSM3

Ideal nMOS I-V Plot


180 nm TSMC process
Ideal Models
= 155(W/L) A/V2
Vt = 0.4 V
VDD = 1.8 V

Ids (A)
400
Vgs = 1.8

300

Vgs = 1.5

200

Vgs = 1.2

100

Vgs = 0.9
Vgs = 0.6
0

0.3

CMOS VLSI Design

0.6

0.9

1.2

1.5

1.8

Vds

MOS Behavior inSlide


DSM4

Simulated nMOS I-V Plot


180 nm TSMC process
BSIM 3v3 SPICE models
I
What differs?

ds

(A)

250

Vgs = 1.8

200

Vgs = 1.5

150

Vgs = 1.2

100

Vgs = 0.9

50

Vgs = 0.6

0
0

0.3

0.6

0.9

1.2

1.5

Vds

CMOS VLSI Design

MOS Behavior inSlide


DSM5

Simulated nMOS I-V Plot


180 nm TSMC process
BSIM 3v3 SPICE models
I (A)
What differs?
250
Less ON current
200
No square law
150
Current increases
100
in saturation
ds

Vgs = 1.8
Vgs = 1.5
Vgs = 1.2
Vgs = 0.9

50

Vgs = 0.6

0
0

0.3

0.6

0.9

1.2

1.5

Vds

CMOS VLSI Design

MOS Behavior inSlide


DSM6

Velocity Saturation
We assumed carrier velocity is proportional to E-field
v = Elat = Vds/L
At high fields, this ceases to be true
Carriers scatter off atoms
Velocity reaches vsat
Electrons: 6-10 x 106 cm/s

Holes: 4-8 x 106 cm/s


Better model
Elat
v
vsat Esat
Elat
1
Esat

CMOS VLSI Design

sat

sat

/2

slope =

Esat

2Esat

3Esat

Elat

MOS Behavior inSlide


DSM7

Vel Sat I-V Effects


Ideal transistor ON current increases with VDD2
2
W Vgs Vt

I ds Cox
Vgs Vt
L
2
2
2

Velocity-saturated ON current increases with VDD


I ds CoxW Vgs Vt vmax

Real transistors are partially velocity saturated


Approximate with -power law model
Ids VDD
1 < < 2 determined empirically
CMOS VLSI Design

MOS Behavior inSlide


DSM8

-Power Model

V
I ds I dsat ds
Vdsat

I dsat

Vgs Vt

cutoff

Vds Vdsat

linear

Vds Vdsat

saturation

I dsat

Pc Vgs Vt
2

Vdsat Pv Vgs Vt

/2

Simulated
-law
Shockley

Ids (A)
400
300

Vgs = 1.8
200

Vgs = 1.5

100

Vgs = 1.2

Vgs = 0.9
Vgs = 0.6

0.3

0.6

0.9

1.2

1.5

CMOS VLSI Design

1.8 V
ds

MOS Behavior inSlide


DSM9

Channel Length Modulation


Reverse-biased p-n junctions form a depletion region
Region between n and p with no carriers
Width of depletion Ld region grows with reverse bias
V
V
GND
Source
Gate
Drain
Leff = L Ld
Depletion Region
Width: L
Shorter Leff gives more current
DD

DD

Ids increases with Vds


Even in saturation

CMOS VLSI Design

n+

L
Leff

n+

p GND

bulk Si

MOS Behavior Slide


in DSM
10

Chan Length Mod I-V


Ids (A)

I ds Vgs Vt 1 Vds
2

400
Vgs = 1.8

300

Vgs = 1.5

200

Vgs = 1.2

100
0

Vgs = 0.9
Vgs = 0.6
0

0.3

0.6

0.9

1.2

1.5

1.8 Vds

= channel length modulation coefficient


not feature size
Empirically fit to I-V characteristics
CMOS VLSI Design

MOS Behavior Slide


in DSM
11

Body Effect
Vt: gate voltage necessary to invert channel
Increases if source voltage increases because
source is connected to the channel
Increase in Vt with Vs is called the body effect

CMOS VLSI Design

MOS Behavior Slide


in DSM
12

Body Effect Model


Vt Vt 0

s Vsb s

s = surface potential at threshold


s 2vT ln

NA
ni

Depends on doping level NA


And intrinsic carrier concentration ni
= body effect coefficient
t
ox 2q si N A
ox

2q si N A
Cox

CMOS VLSI Design

MOS Behavior Slide


in DSM
13

OFF Transistor Behavior


What about current in cutoff?
Simulated results
I
1 mA
What differs?
Sub100 A
threshold
Current doesnt go 10 A Region
1 A
to 0 in cutoff
100 nA
ds

10 nA

Subthreshold
Slope

1 nA
100 pA
10 pA
0

0.3

Saturation
Region

Vds = 1.8

Vt
0.6

0.9

1.2

1.5

1.8

Vgs

CMOS VLSI Design

MOS Behavior Slide


in DSM
14

Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF
Junction leakage
Reverse-biased PN junction diode current
Gate leakage
Tunneling through ultrathin gate dielectric
Subthreshold leakage is the biggest source in
modern transistors

CMOS VLSI Design

MOS Behavior Slide


in DSM
15

Subthreshold Leakage
Subthreshold leakage exponential with Vgs
Vgs Vt

I ds I ds 0e

Vds
vT

1 e

nvT

I ds 0 vT2 e1.8

n is process dependent, typically 1.4-1.5

CMOS VLSI Design

MOS Behavior Slide


in DSM
16

DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt

Vt Vt Vds

VVV

ttds

High drain voltage causes subthreshold leakage


to ________.

CMOS VLSI Design

MOS Behavior Slide


in DSM
17

DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt

Vt Vt Vds

VVV

ttds

High drain voltage causes subthreshold leakage


to increase.

CMOS VLSI Design

MOS Behavior Slide


in DSM
18

Junction Leakage
Reverse-biased p-n junctions have some leakage

ID IS e

VD
vT

Is depends on doping levels


And area and perimeter of diffusion regions
Typically < 1 fA/m2

p+

n+

n+

p+

p+

n+

n well
p substrate

CMOS VLSI Design

MOS Behavior Slide


in DSM
19

Gate Leakage
Carriers may tunnel thorough very thin gate oxides
Predicted tunneling current (from [Song01])
109

tox
VDD trend

0.6 nm
0.8 nm

JG (A/cm )

106
103

1.0 nm
1.2 nm

100

1.5 nm
1.9 nm

10-3
10-6
10-9
0

Negligible for older processes


May soon be critically important
CMOS VLSI Design

0.3

0.6

0.9

1.2

1.5

1.8

VDD

MOS Behavior Slide


in DSM
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Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces Vt
ION ___________ with temperature
IOFF ___________ with temperature

CMOS VLSI Design

MOS Behavior Slide


in DSM
21

Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces Vt
ION decreases with temperature
IOFF increases with temperature
I ds
increasing
temperature

Vgs

CMOS VLSI Design

MOS Behavior Slide


in DSM
22

So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for

Supply voltage choice


Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation

CMOS VLSI Design

MOS Behavior Slide


in DSM
23

Parameter Variation

fast

Transistors have uncertainty in parameters


Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values
Fast (F)

FF

SF

pMOS

Leff: ______
Vt: ______

TT

FS
slow

tox: ______

SS

Slow (S): opposite


Not all parameters are independent
for nMOS and pMOS
CMOS VLSI Design

slow

nMOS

fast

MOS Behavior Slide


in DSM
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Parameter Variation

fast

Transistors have uncertainty in parameters


Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values
Fast (F)

FF

SF

pMOS

Leff: short
Vt: low

TT

FS
slow

tox: thin

SS

Slow (S): opposite


Not all parameters are independent
for nMOS and pMOS
CMOS VLSI Design

slow

nMOS

fast

MOS Behavior Slide


in DSM
25

Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: ____
T: ____
Corner

Voltage

Temperature

1.8

70 C

F
T
S

CMOS VLSI Design

MOS Behavior Slide


in DSM
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Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: high
T: low
Corner

Voltage

Temperature

1.98

0C

1.8

70 C

1.62

125 C

CMOS VLSI Design

MOS Behavior Slide


in DSM
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Process Corners
Process corners describe worst case variations
If a design works in all corners, it will probably
work for any variation.
Describe corner with four letters (T, F, S)
nMOS speed
pMOS speed
Voltage
Temperature

CMOS VLSI Design

MOS Behavior Slide


in DSM
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Important Corners
Some critical simulation corners include

Purpose

nMOS

pMOS

VDD

Temp

Cycle time
Power
Subthrehold
leakage
Pseudo-nMOS

CMOS VLSI Design

MOS Behavior Slide


in DSM
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Important Corners
Some critical simulation corners include

Purpose

nMOS

pMOS

VDD

Temp

Cycle time

Power

Subthrehold
leakage

Pseudo-nMOS S

CMOS VLSI Design

MOS Behavior Slide


in DSM
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