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CMOS VLSI
Design
Outline
Transistor I-V Review
Nonideal Transistor Behavior
Velocity Saturation
Channel Length Modulation
Body Effect
Leakage
Temperature Sensitivity
Process and Environmental Variations
Process Corners
Vgs Vt
V
I ds Vgs Vt ds Vds Vds Vdsat
2
Vgs Vt
Vds Vdsat
2
CMOS VLSI Design
cutoff
linear
saturation
Ids (A)
400
Vgs = 1.8
300
Vgs = 1.5
200
Vgs = 1.2
100
Vgs = 0.9
Vgs = 0.6
0
0.3
0.6
0.9
1.2
1.5
1.8
Vds
ds
(A)
250
Vgs = 1.8
200
Vgs = 1.5
150
Vgs = 1.2
100
Vgs = 0.9
50
Vgs = 0.6
0
0
0.3
0.6
0.9
1.2
1.5
Vds
Vgs = 1.8
Vgs = 1.5
Vgs = 1.2
Vgs = 0.9
50
Vgs = 0.6
0
0
0.3
0.6
0.9
1.2
1.5
Vds
Velocity Saturation
We assumed carrier velocity is proportional to E-field
v = Elat = Vds/L
At high fields, this ceases to be true
Carriers scatter off atoms
Velocity reaches vsat
Electrons: 6-10 x 106 cm/s
sat
sat
/2
slope =
Esat
2Esat
3Esat
Elat
I ds Cox
Vgs Vt
L
2
2
2
-Power Model
V
I ds I dsat ds
Vdsat
I dsat
Vgs Vt
cutoff
Vds Vdsat
linear
Vds Vdsat
saturation
I dsat
Pc Vgs Vt
2
Vdsat Pv Vgs Vt
/2
Simulated
-law
Shockley
Ids (A)
400
300
Vgs = 1.8
200
Vgs = 1.5
100
Vgs = 1.2
Vgs = 0.9
Vgs = 0.6
0.3
0.6
0.9
1.2
1.5
1.8 V
ds
DD
n+
L
Leff
n+
p GND
bulk Si
I ds Vgs Vt 1 Vds
2
400
Vgs = 1.8
300
Vgs = 1.5
200
Vgs = 1.2
100
0
Vgs = 0.9
Vgs = 0.6
0
0.3
0.6
0.9
1.2
1.5
1.8 Vds
Body Effect
Vt: gate voltage necessary to invert channel
Increases if source voltage increases because
source is connected to the channel
Increase in Vt with Vs is called the body effect
s Vsb s
NA
ni
2q si N A
Cox
10 nA
Subthreshold
Slope
1 nA
100 pA
10 pA
0
0.3
Saturation
Region
Vds = 1.8
Vt
0.6
0.9
1.2
1.5
1.8
Vgs
Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF
Junction leakage
Reverse-biased PN junction diode current
Gate leakage
Tunneling through ultrathin gate dielectric
Subthreshold leakage is the biggest source in
modern transistors
Subthreshold Leakage
Subthreshold leakage exponential with Vgs
Vgs Vt
I ds I ds 0e
Vds
vT
1 e
nvT
I ds 0 vT2 e1.8
DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt
Vt Vt Vds
VVV
ttds
DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt
Vt Vt Vds
VVV
ttds
Junction Leakage
Reverse-biased p-n junctions have some leakage
ID IS e
VD
vT
p+
n+
n+
p+
p+
n+
n well
p substrate
Gate Leakage
Carriers may tunnel thorough very thin gate oxides
Predicted tunneling current (from [Song01])
109
tox
VDD trend
0.6 nm
0.8 nm
JG (A/cm )
106
103
1.0 nm
1.2 nm
100
1.5 nm
1.9 nm
10-3
10-6
10-9
0
0.3
0.6
0.9
1.2
1.5
1.8
VDD
Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces Vt
ION ___________ with temperature
IOFF ___________ with temperature
Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces Vt
ION decreases with temperature
IOFF increases with temperature
I ds
increasing
temperature
Vgs
So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for
Parameter Variation
fast
FF
SF
pMOS
Leff: ______
Vt: ______
TT
FS
slow
tox: ______
SS
slow
nMOS
fast
Parameter Variation
fast
FF
SF
pMOS
Leff: short
Vt: low
TT
FS
slow
tox: thin
SS
slow
nMOS
fast
Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: ____
T: ____
Corner
Voltage
Temperature
1.8
70 C
F
T
S
Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: high
T: low
Corner
Voltage
Temperature
1.98
0C
1.8
70 C
1.62
125 C
Process Corners
Process corners describe worst case variations
If a design works in all corners, it will probably
work for any variation.
Describe corner with four letters (T, F, S)
nMOS speed
pMOS speed
Voltage
Temperature
Important Corners
Some critical simulation corners include
Purpose
nMOS
pMOS
VDD
Temp
Cycle time
Power
Subthrehold
leakage
Pseudo-nMOS
Important Corners
Some critical simulation corners include
Purpose
nMOS
pMOS
VDD
Temp
Cycle time
Power
Subthrehold
leakage
Pseudo-nMOS S