Semiconductor

Memories
Lecture 1: May 10, 2006
EE Summer Camp
Abhinav Agarwal

Outline

Concept/need of memory
Parameters
Types/classification
Basic features
Basic Cell circuits
Peripheral circuitry

Concept

Data storage essential for processing

Binary storage
Switches
Write

'0'
Read
'1'

How do you implement this in Hardware?

Requirements

Easy reading
Easy Writing
High density
Speed, more speed and still more speed

Memory Chip Configuration

Row Address
N bits

2 Cells
Memory Cell Array

Complete Address
N+M Bits
WL

Control
Signals

Row Dec

Dout

I/O Interface

Din

Cell

DL

din

I/O Control

dout
Column Dec.

Column Address
M Bits

2 Cells

Semiconductor Memory Classification

Read-Write Memory

Random
Access

Non-Random
Access

SRAM

FIFO

DRAM

LIFO

Non-Volatile
Read-Write
Memory
EPROM
2

E PROM

Read-Only Memory

Mask-Programmed
Programmable (PROM)

FLASH

Shift Register
CAM

Digital Integrated Circuits2nd

Memories

RAM

Random write and read operation for any cell

Volatile data
Most of computer memory
DRAM

Low Cost
High Density
Medium Speed

SRAM

High Speed
Ease of use
Medium Cost

ROM

Non-volatile Data
Method of Data Writing
Mask ROM

Data written during chip fabrication

PROM

Fuse ROM: Non-rewritable

EPROM: Erase data by UV rays
EEPROM: Erase and write through electrical means

Speed 2-3 times slower than RAM

Upper limit on write operations
Flash Memory High density, Low Cost

Basic Cells

DRAM

SRAM
VDD

WL
WL

DL
DL

WL

DL

Static CAM Memory Cell

Bit

Bit

Bit

Bit
Bit

Word
CAM

M4

CAM

Word

Word
CAM

Bit

CAM

M8

M9

M6

M7

S
M3

Match

int

M5

S
M2
M1

Wired-NOR Match Line

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Memories

CAM in Cache Memory

CAM

SRAM

ARRAY

ARRAY

Input Drivers

Address

Digital Integrated Circuits2nd

Tag

Sense Amps / Input Drivers

Hit

R/W

Data

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ROM

Fuse ROM

WL

EEPROM
WL

Floating Gate

DL

DL

MOS NAND ROM

V DD
Pull-up devices
BL [0]

BL [1]

BL [2]

BL [3]

WL [0]

WL [1]
WL [2]

WL [3]

All word lines high by default with exception of selected row

Digital Integrated Circuits2nd

Memories

Non-Volatile Memories
The Floating-gate transistor (FAMOS)
Floating gate

Gate

Source

Drain
G

tox
tox
n+
Substrate

Device cross-section

Digital Integrated Circuits2nd

n+_

Schematic symbol

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Floating-Gate Transistor Programming

20 V

10 V 5 V 20 V
S

5V

0V

Avalanche injection

Digital Integrated Circuits2nd

5V

0V
D

Removing programming
voltage leaves charge trapped

2.5 V

5V
D

Programming results in
higher V T .

Memories

A Programmable-Threshold Transistor
0-state

1-state

ON
DV T

OFF
V WL

Digital Integrated Circuits2nd

V GS

Memories

Periphery
Decoders
Sense Amplifiers
Input/Output Buffers
Control / Timing Circuitry

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Memories

Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder

NOR Decoder

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Hierarchical Decoders
Multi-stage implementation improves performance

WL 1

WL 0

A 0A 1 A 0A 1 A 0A 1 A 0A 1

A 2A 3 A 2A 3 A 2A 3 A 2A 3

A1 A0

A0

A1

Digital Integrated Circuits2nd

A3 A2

A2

A3

NAND decoder using

2-input pre-decoders

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Sense Amplifiers
V
tp = C
---------------Iav
large

make V as small
as possible
small

Idea: Use Sense Amplifer

small
transition

s.a.
input

Digital Integrated Circuits2nd

output

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Sense Amp Operation

V BL

V(1)
V PRE

DV(1)

V(0)
Sense amp activated
Word line activated

Digital Integrated Circuits2nd

Memories

Differential Sense Amplifier

V DD
M3

M4
y

M1

bit

SE

M2

Out

bit

M5

Directly applicable to
SRAMs
Digital Integrated Circuits2nd

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Reliability and Yield

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References

Digital Integrated Circuits, 2nd Edition, Jan Rabaey,

Anantha Chandrakasan, Borivoje Nikolic
Chapter 12 http://bwrc.eecs.berkeley.edu/IcBook/slides.htm

Sedra & Smith, Microelectronic Circuits, 4th Edition,

Chapter 13

Section 13.9, 13.10, 13.11, 13.12

VLSI Memory Chip Design, Kiyoo Itoh