RECONFIGURABLE

COMPUTING HARDWARE
DEVICE ARCHITECTURE
Kalyani S. Bhosale
Roll No ME13EM05
Under the guidance of
Prof. R. R. Itkarkar

Field Programmable Gate Array (FPGA)

consists of three main parts:

a set of programmable logic cells also called logic

blocks or configurable logic blocks (CLBs)

a programmable interconnection network

a set of input and output cells around the device

Every function to be implemented in FPGA is partitioned
in modules, each of which can be implemented in a logic
block.
The logic blocks are then connected together using the
programmable interconnection.
All three basic components of an FPGA can be
programmed by the user in the field.
FPGAs can be programmed once or several times
depending on the technology used

Technology

The technology defines how the different

blocks
(logic
blocks,
interconnect,input/output) are physically
realized.
Basically,
two
major
technologies exist:
Antifuse - limited to the realization
of interconnections
Memory-based - used for the
computation as well as the
interconnections
(eg: the SRAM, the EEPROM and

Antifuse Technology
An antifusebased FPGA uses special antifuses included at each
connection customization point.
The two-terminal elements are connected to the upper and lower
layer of the antifuse, in the middle of which a dielectric is placed.
In its initial state, the high resistance of the dielectric does not
allow any current to flow between the two layers.
Applying a high voltage causes large power dissipation in a small
area, which melts the dielectric.
This operation drastically reduces the resistance and a link can be
built, which permanently connects the two layers.
The two types of antifuses actually commercialized are:

The Programmable Low-Impedance Circuit Element (PLICE)

(Actel)
The Metal Antifuse also called ViaLink (QuickLogic)

SRAM

SRAM is used to configure the logic

blocks and the connection as well.
most widely used
In an SRAM-based FPGA, the states of
the logic blocks, i.e. their functionality
bits
as
well
as
that
of
the
interconnections, are controlled by the
output of SRAM cells

EPROM

Erasable
programmable
read
only
memory (EPROM) devices are based on
a floating gate. The device can be
permanently programmed by applying a
high voltage between the control gate
and the drain of the transistor.

EEPROM

In EEPROM-based devices, two or more

transistors are typically used in a ROM
cell: one access and one programmed
transistor.
The programmed transistor performs the
same function as the floating gate in an
EPROM, with both charge and discharge
being done electrically.

FLASH - EEPROM

In the flash-EEPROMs that are used, two

transistors share the floating gate, which store the
programming information.
The sensing transistor is only used for writing and
verification of the floating gate voltage whereas
the other is used as switch.
This can be used to connect or disconnect routing
nets to or from the configured logic. The switch is
also used to erase the floating gate.

References

Christophe Bobda, Introduction to Reconfigurable

Computing, Springer Publication
A. Azarian, M. Ahmadi, Reconfigurable Computing
Architecture Survey and introduction, 978-1-42444520-2/09/2009 IEEE