Vlsi Technology

Digital Integrated
Circuits
Jan M. Rabaey
AAnantha
Design
Perspective
Chandrakasan
Borivoje Nikolic
Semiconductor
Memories
December 20, 2002
Digital Integrated Circuits2nd
Memories
Chapter Overview
Memory Classification
Memory Architectures
The Memory Core
Periphery
Reliability
Case Studies
Memories
Semiconductor Memory Classification

Read-Write Memory
Random
Access
Non-Random
Access
SRAM
FIFO
DRAM
LIFO
Non-Volatile
Read-Write
Memory
EPROM
2
E PROM
Read-Only Memory
Mask-Programmed
Programmable (PROM)
FLASH
Shift Register
CAM
Memories
Memory Timing: Definitions

Read cycle
READ
Read access
Read access
Write cycle
WRITE
Write access
Data valid
DATA
Data written
Memories
Memory Architecture: Decoders

M bits
S0
S1
S2
SN2 2
SN2 1
M bits
S0
Word 0
Word 1
Word 2
Storage
cell
Word 0
A0
Word 1
A1
Word 2
Storage
cell
AK 2 1
WordN2 2
WordN2 2
WordN2 1
WordN2 1
K 5 log2N
Input-Output
(M bits)
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals
Input-Output
(M bits)
Decoder reduces the number of select signals
K = log2N
Memories
Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH
AK
AK1 1
AL 2 1
Bit line
Row Decoder
2L 2 K
Word line
M.2K
Sense amplifiers / Drivers
A0
AK2 1
Column decoder
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Input-Output
(M bits)
Memories
Hierarchical Memory Architecture

Block 0
Blocki
BlockP 2 1
Row
address
Column
address
Block
address
Global data bus

Control
circuitry
Block selector
Global
amplifier/driver
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
Memories
Block Diagram of 4 Mbit SRAM

Clock
generator
Z-address
buffer
X-address
buffer
Predecoder and block selector

Bit line load
Transfer gate
Column decoder
Sense amplifier and write driver
CS, WE
buffer
I/O
buffer
x1/x4
controller
Y-address
buffer
[Hirose90]
X-address
buffer
Memories
Data (64 bits)
Commands
Comparand
Priority Encoder
CAM Array
2 words3 64 bits
9
C ontrol LogicR/W Address (9 bits)
2 Validity Bits
Mask
Address Decoder
I/O Bufers
Contents-Addressable Memory
Memories
Memory Timing: Approaches

Address
bus
Row Address
Column Address
RAS
Address
Bus
Address
Address transition
initiates memory operation
CAS
RAS-CAS timing
DRAM Timing
Multiplexed Adressing
SRAM Timing
Self-timed
Memories
Read-Only Memory Cells

BL
BL
BL
VDD
WL
WL
WL
BL
WL
BL
WL
BL
WL
GND
Diode ROM
MOS ROM 1
MOS ROM 2
Memories
MOS OR ROM
BL[0]
BL[1]
BL[2]
BL[3]
WL[0]
V DD
WL[1]
WL[2]
V DD
WL[3]
V bias
Pull-down loads
Memories
MOS NOR ROM

V DD
Pull-up devices
WL[0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0]
BL [1]
BL [2]
BL [3]
Memories
MOS NOR ROM Layout

Cell (9.5 x 7)
Programmming using the

Active Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Memories
MOS NOR ROM Layout

Cell (11 x 7)
Programmming using
the Contact Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Memories
MOS NAND ROM

V DD
Pull-up devices
BL [0]
BL [1]
BL [2]
BL [3]
WL [0]
WL [1]
WL [2]
WL [3]
All word lines high by default with exception of selected row

Memories
MOS NAND ROM Layout

Cell (8 x 7)
Programmming using
the Metal-1 Layer Only
No contact to VDD or GND necessary;
drastically reduced cell size
Loss in performance compared to NOR ROM
Polysilicon
Diffusion
Metal1 on Diffusion
Memories
NAND ROM Layout

Cell (5 x 6)
Programmming using
Implants Only
Polysilicon
Threshold-altering
implant
Metal1 on Diffusion
Memories
Equivalent Transient Model for MOS NOR ROM

V DD
Model for NOR ROM
BL
rword
WL
Cbit
cword
Word line parasitics

Wire capacitance and gate capacitance
Wire resistance (polysilicon)
Bit line parasitics

Resistance not dominant (metal)
Drain and Gate-Drain capacitance
Memories
Equivalent Transient Model for MOS NAND ROM

V DD
Model for NAND ROM
BL
CL
r bit
WL
r word
cbit
cword
Word line parasitics

Similar to NOR ROM
Bit line parasitics

Resistance of cascaded transistors dominates
Drain/Source and complete gate capacitance
Memories
Decreasing Word Line Delay

Driver
WL
Polysilicon word line
Metal word line
(a) Driving the word line from both sides

Metal bypass
WL
K cells
Polysilicon word line
(b) Using a metal bypass

(c) Use silicides
Memories
Precharged MOS NOR ROM

V DD
f pre
Precharge devices
WL [0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0]
BL [1]
BL [2]
BL [3]
PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.
Memories
Non-Volatile Memories
The Floating-gate transistor (FAMOS)
Floating gate
Gate
Source
Drain
G
tox
tox
n+
Substrate
Device cross-section
n+_
Schematic symbol
Memories
Floating-Gate Transistor Programming

20 V
0V
10 V 5 V 20 V
S
Avalanche injection
25 V
S
5V
0V
D
Removing programming
voltage leaves charge trapped
2 2.5 V
S
5V
D
Programming results in
higher V T .
Memories
A Programmable-Threshold Transistor
0-state
1-state
ON
DV T
OFF
V WL
V GS
Memories
FLOTOX EEPROM
Gate
Floating gate
I
Drain
Source
2030 nm
V GD
-10 V
10 V
n1
n1
Substrate
p
10 nm
FLOTOX transistor
Fowler-Nordheim
I-V characteristic
Memories
EEPROM Cell
BL
WL
VDD
Absolute threshold control

is hard
Unprogrammed transistor
might be depletion
2 transistor cell
Memories
Flash EEPROM
Control gate
Floating gate
erasure
n1 source
Thin tunneling oxide
programming
n1 drain
p-substrate
Many other options

Memories
Cross-sections of NVM cells
Flash
EPROM
Courtesy Intel
Memories
Basic Operations in a NOR Flash Memory

Erase
cell
12 V
BL 0
array
BL 1
0V
WL 0
0V
WL 1
open
open
Memories

Write
12 V
G
S
BL 0
BL 1
6V
12 V
WL 0
0V
WL 1
6V
0V
Memories

Read
5V
G
BL 0
1V
5V
WL 0
0V
WL 1
1V
BL 1
0V
Memories
NAND Flash Memory

Word line(poly)
Gate
Unit Cell
ONO
Gate
Oxide
FG
Source line
(Diff. Layer)
Courtesy Toshiba
Memories
NAND Flash Memory

Select transistor
Word lines
Active area
STI
Bit line contact
Source line contact

Courtesy Toshiba
Memories
Characteristics of State-of-the-art NVM
Memories
Read-Write Memories (RAM)

STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
Memories
6-transistor CMOS SRAM Cell

WL
V DD
M2
M5
Q
M1
BL
M4
Q
M6
M3
BL
Memories
CMOS SRAM Analysis (Read)

WL
V DD
M4
BL
Q= 0
M5
V DD
Cbit
M1
Q= 1
V DD
BL
M6
V DD
Cbit
Memories
CMOS SRAM Analysis (Read)

1.2
Voltage Rise (V)
1
0.8
0.6
0.4
0.2
0
0
0.5
1 1.2 1.5 2
Cell Ratio (CR)
2.5
Memories
CMOS SRAM Analysis (Write)

WL
V DD
M4
M5
Q= 1
M1
BL = 1
M6
Q= 0
VDD
BL = 0
Memories
CMOS SRAM Analysis (Write)
Memories
6T-SRAM Layout
VDD
M2
M4
Q
M1
M3
GND
M5
BL
M6
WL
BL
Memories
Resistance-load SRAM Cell

WL
RL
M3
BL
V DD
RL
M1
M2
M4
BL
Static power dissipation -- Want R L large

Bit lines precharged to V DD to address t p problem
Memories
SRAM Characteristics
Memories
3-Transistor DRAM Cell

BL 1
BL 2
WWL
WWL
RWL
M3
X
M1
CS
M2
RWL
V DD 2 V T
X
BL 1
BL 2
V DD
DV
V DD 2 V T
No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a 1 = VWWL-VTn
Memories
3T-DRAM Layout
BL2
BL1
GND
RWL
M3
M2
WWL
M1
Memories
1-Transistor DRAM Cell

BL
Write 1
WL
Read 1
WL
M1
CS
V DD 2 V T
X GND
V DD
BL
V DD /2
V
sensing
CBL
Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
V = VBL V PRE = V BIT V PRE -----------C S + CBL
Voltage swing is small; typically around 250 mV.
Memories
DRAM Cell Observations

1T
DRAM requires a sense amplifier for each bit line, due

to charge redistribution read-out.
DRAM memory cells are single ended in contrast to
SRAM cells.
The read-out of the 1T DRAM cell is destructive; read
and refresh operations are necessary for correct
operation.
Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
When writing a 1 into a DRAM cell, a threshold
voltage is lost. This charge loss can be circumvented by
bootstrapping the word lines to a higher value than VDD
Memories
Sense Amp Operation

V BL
V(1)
V PRE
DV(1)
V(0)
Sense amp activated
Word line activated
Memories
1-T DRAM Cell

Capacitor
M 1 word
line
Metal word line

Poly
n+
Field Oxide
n+
Poly
SiO2
Inversion layer
induced by
plate bias
Cross-section
Diffused
bit line
Polysilicon
gate
Polysilicon
plate
Layout
Uses Polysilicon-Diffusion Capacitance

Expensive in Area
Memories
SEM of poly-diffusion capacitor 1T-DRAM
Memories
Advanced 1T DRAM Cells

Word line
Insulating Layer
Cell plate
Capacitor dielectric layer
Cell Plate Si
Capacitor Insulator
Refilling Poly
Storage Node Poly
Transfer gate
Isolation
Storage electrode
Si Substrate
2nd Field Oxide
Trench Cell
Stacked-capacitor Cell
Memories
Static CAM Memory Cell

Bit
Bit
Bit
Bit
Bit
Word
CAM
M4
CAM
Word
Word
CAM
Bit
CAM
M8
M9
M6
M7
S
M3
Match
int
M5
S
M2
M1
Wired-NOR Match Line
Memories
CAM in Cache Memory
CAM
SRAM
ARRAY
ARRAY
Input Drivers
Address
Tag
Sense Amps / Input Drivers
Hit
R/W
Data
Memories
Periphery
Decoders
Sense Amplifiers
Input/Output Buffers
Control / Timing Circuitry
Memories
Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
Memories
Hierarchical Decoders
Multi-stage implementation improves performance
WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1
A 2A 3 A 2A 3 A 2A 3 A 2A 3
A1 A0
A0
A1
A3 A2
A2
A3
NAND decoder using

2-input pre-decoders
Memories
Dynamic Decoders
Precharge devices
GND
VDD
GND
WL 3
VDD
WL 3
WL 2
WL 2
VDD
WL 1
WL 1
V DD
WL 0
WL 0
VDD
A0
A0
A1
A1
2-input NOR decoder
A0
A0
A1
A1
2-input NAND decoder
Memories
4-input pass-transistor based column

decoder
BL
BL
BL
BL
0
A0
S0
S1
S2
A1
S3
Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count
Memories
4-to-1 tree based column decoder

BL 0 BL 1 BL 2 BL 3
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches
Memories
Decoder for circular shift-register

V DD
V DD
V DD
WL 0
R
V DD
V DD
WL 1
f
V DD
WL 2
f
V DD
Memories
Sense Amplifiers
V
tp = C
---------------Iav
large
make V as small
as possible
small
Idea: Use Sense Amplifer

small
transition
s.a.
input
output
Memories
Differential Sense Amplifier

V DD
M3
M4
y
M1
bit
SE
M2
Out
bit
M5
Directly applicable to
SRAMs
Memories
Differential Sensing SRAM

V DD
PC
BL
V DD
BL
V DD
EQ
WL i
M3
M1
SE
V DD
M4
M2
M5
2
x
2
x
x
SE
SE
SRAM cell i
Dif.
x Sense2
x
Amp
V DD
Output
SE
Output
(a) SRAM sensing scheme
(b) two stage diferential amplifier
Memories
Latch-Based Sense Amplifier (DRAM)

EQ
BL
BL
VDD
SE
SE
Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
Memories
Charge-Redistribution Amplifier
V ref
VL
M2
M3
M1
Clarge
VS
C small
Transient Response
2.5
Concept
2.0
VS
V in
1.5
1.0
0.5
0.0
0.0
VL
V ref5 3V
1.00
2.00
time(nsec)
3.00
(b) Transient response

Memories
Charge-Redistribution Amplifier
V
EPROM
DD
SE
Load
M4
Out
V casc
M3
Cascode
device
Cout
Ccol
WLC
Column
decoder
M2
BL
WL
M1
CBL
EPROM
array
Memories
Single-to-Differential Conversion
WL
BL
x
Cell
Dif.
S.A.
2
x
1
2
V ref
Output
How to make a good Vref?

Memories
Open bitline architecture with

dummy cells
EQ
L
L1
L0
V DD
R0
R1
SE
BLL
CS
CS
BLR
CS
Dummy cell
SE
CS
CS
CS
Dummy cell
Memories
DRAM Read Process with Dummy Cell

3
2
BL
BL
1
BL
BL
t (ns)
t (ns)
reading 1
reading 0
3
EQ
WL
2
SE
1
t (ns)
control signals
Memories
Voltage Regulator
VDD
Mdrive
VDL
VREF
Equivalent Model
Vbias
VREF
Mdrive
VDL
Memories
Charge Pump
V DD
CLK
VB
M1
B
2V DD 2 V T
V DD 2 V T
0V
Cpump
M2
V load
Cload
V load
0V
Memories
DRAM Timing
Memories
RDRAM Architecture
Bus
Clocks
Data
bus
Column
Row
k3 l
memory
array
demux
packet dec.
demux
packet dec.
Memories
Address Transition Detection

V DD
A0
DELAY
td
A1
DELAY
td
A N2 1
DELAY
td
ATD
ATD
Memories
Reliability and Yield
Memories
Sensing Parameters in DRAM

1000
V smax(mv)
100
CD(1F)
CS(1F)
Q S(1C)
10
VDD (V)
Q S 5 CS VDD /2
V smax5 QS/(C S 1 CD )
4K
64K 1M 16M 256M 4G 64G

Memory Capacity (bits
/chip)
From [Itoh01]
Memories
Noise Sources in 1T DRam

BL
CWBL
substrate Adjacent BL
a-particles
WL
leakage
CS
electrode
Ccross
Memories
Open Bit-line Architecture Cross Coupling
EQ
WL 1
WL 0
BL
WL
CWBL D
CWBL
WL D
WL 1
WL 0
BL
CBL
C
Sense
Amplifier
CBL
Memories
Folded-Bitline Architecture
WL 1
BL
WL 0 C
WBL
WL 0
WL D
WL D
CBL
C
BL
WL 1
x
C
CBL
Sense
EQ Amplifier
x
CWBL
Memories
Transposed-Bitline Architecture
Ccross
BL 9
BL
SA
BL
BL 99
(a) Straightforward bit-line routing
Ccross
BL 9
BL
SA
BL
BL 99
(b) Transposed bit-line architecture
Memories
Alpha-particles (or Neutrons)

a-particle
WL
V DD
BL
n1
SiO2
1
1
2
2
1
1
2
2
1 Particle ~ 1 Million Carriers

Memories
Yield
Yield curves at different stages of process maturity

(from [Veendrick92])
Memories
Redundancy
Row
Address
Redundant
rows
:
Redundant
columns
Memory
Array
Column Decoder
Fuse
Bank
Column
Address
Memories
Error-Correcting Codes
Example: Hamming Codes
e.g. B3 Wrong
with
1
1
=3
Memories
Redundancy and Error Correction
Memories
Sources of Power Dissipation in

Memories V
DD
I DD 5 S C iDV if1S I DCP
CHIP
nCDE V INT f
selected miact
C PT V INT f
I DCP
n
ROW
DEC
PERIPHERY
non-selected m(n2 1)ihld

ARRAY
mCDE V INT f
COLUMN DEC
V SS
From [Itoh00]
Memories
Data Retention in SRAM

1.30u
1.10u
0.13m m CMOS
Ileakage
900n
700n
500n
Factor 7
300n
0.18m m CMOS
100n
0.00
.600
1.20
1.80
VDD
SRAM leakage increases with technology scaling

Memories
Suppressing Leakage in SRAM

V DD
V DD
low-threshold transistor
V DDL
sleep
V DD,int
sleep
V DD,int
SRAM
cell
SRAM
cell
sleep
SRAM
cell
SRAM
cell
SRAM
cell
V SS,int
Inserting Extra Resistance

SRAM
cell
Reducing the supply voltage

Memories
Data Retention in DRAM

101
100
I ACT
Current (A)
21
10
I AC
22
10
102 3
Cycle time : 150 ns
T 5 75 C,S
24
10
I DC
25
10
26
10
15M
64M
255M
1G
4G
15G
64G
1.0
0.8
0.16
0.13
Capacity (bit)
3.3
2.5
2.0
1.5
1.2
Operating voltage (V)

0.53
0.40
0.32
0.24
0.19
Extrapolated threshold voltage at 25 C (V)
From [Itoh00]
Memories
Case Studies
Programmable
Logic Array
SRAM
Flash
Memory
Memories
PLA versus ROM

Programmable Logic Array
structured approach to random logic
two level logic implementation
NOR-NOR (product of sums)
NAND-NAND (sum of products)
IDENTICAL TO ROM!
Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance of PLAs has drastically reduced
1. slow
2. better software techniques (mutli-level logic
synthesis)
But
Memories
Programmable Logic Array

Pseudo-NMOS PLA
GND
GND
GND
V DD
GND
GND
GND
GND
V DD
X0
X0
X1
AND-plane
X1
X2
X2
f0
f1
OR-plane
Memories
Dynamic PLA
f AND
V DD
GND
f OR
f OR
f AND
V DD
X0
X0
X1
X1
AND-plane
X2
X2
f0
f1 GND
OR-plane
Memories
Clock Signal Generation

for self-timed dynamic PLA
f
f AND
Dummy AND row

f AND
tpre teval
f AND
f OR
Dummy AND row
f OR
(a) Clock signals
(b) Timing generation circuitry
Memories
PLA Layout
AndPlane
VDD
x0 x0 x1 x1 x2 x2
Pullupdevices
OrPlane
GND
f0 f1
Pullupdevices
Memories
4 Mbit SRAM
Hierarchical Word-line Architecture
Global word line
Sub-global word line
Local
word line
Block group
select
Block
select
Local
word line
Memory cell
Block 0
Block 1
Block
select
Block 2...
Memories
Bit-line Circuitry
Block
select
Bit-line
load
ATD
BEQ
Local WL
Memory cell
B/T
B/T
CD
CD
CD
I/O line
Sense amplifier
I/O
I/O
Memories
Sense Amplifier (and Waveforms)

Address
I /O
I /O
ATD
SEQ
Block
select
ATD
BEQ
BS
SA
BS
Vdd
I/O Lines
GND
SA
SEQ
SEQ
SEQ
SEQ
SEQ
Vdd
DATA
Dei
SA, SA
GND
DATA
BS
Data-cut
Memories
1 Gbit Flash Memory

BL16996 BL16897
BL33791
SGD
WL31
WL0
SGS
Block0
Block1023
BLT0
BLT1
Data Caches
(10241 32)3 8
Block1023
Bit Line Control Circuit
Sense Latches
(10241 32)3 8
I/O
Block0
Word Line Driver
BL0 BL1 BL16895
Word Line Driver

Word Line Driver
512Mb Memory Array
Word Line Driver
512Mb Memory Array
Sense Latches
(10241 32)3 8
Data Caches
(10241 32)3 8
From [Nakamura02]
Memories
Number of memory cells
Writing Flash Memory

Verify level5 0.8 V Word-line level5 4.5 V
108
106
104
102
Result of 4 times
program
0V 1V 2V 3V 4V
Vt of memory cells
(a)
1V
2V
3V
4V
Vt of memory cells
Evolution of thresholds
100
0V
Final Distribution
From [Nakamura02]
Memories
Charge pump
2kB Page buffer & cache
10.7mm
125mm2 1Gbit NAND Flash Memory

32 word lines
x 1024 blocks
16896 bit lines
11.7mm
From [Nakamura02]
Memories
125mm2 1Gbit NAND Flash Memory
Technology
Technology
0.13m
0.13m p-sub
p-sub CMOS
CMOStriple-well
triple-well
1poly,
1poly,1polycide,
1polycide, 1W,
1W,2Al
2Al
Cell
0.077m2
Cellsize
size
0.077m2
Chip
125.2mm2
Chipsize
size
125.2mm2
Organization
Organization 2112
2112xx8b
8bxx64
64page
pagexx1k
1kblock
block
Power
Power supply
supply 2.7V-3.6V
2.7V-3.6V
Cycle
50ns
Cycle time
time
50ns
Read
25s
Readtime
time
25s
Program
Programtime
time 200s
200s //page
page
Erase
2ms
Erasetime
time
2ms// block
block
From [Nakamura02]
Memories
Semiconductor Memory Trends

(up to the 90s)
Memory Size as a function of time: x 4 every three years

Memories

(updated)
From [Itoh01]
Memories
Trends in Memory Cell Area
From [Itoh01]
Memories
Technology feature size for different SRAM generations

Memories

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Digital Integrated

Semiconductor Memory Classification

Digital Integrated Circuits2nd

Memory Timing: Definitions

Digital Integrated Circuits2nd

Memory Architecture: Decoders

Digital Integrated Circuits2nd

Array-Structured Memory Architecture

Digital Integrated Circuits2nd

Hierarchical Memory Architecture

Global data bus

Block Diagram of 4 Mbit SRAM

Predecoder and block selector

Digital Integrated Circuits2nd

Data (64 bits)

Digital Integrated Circuits2nd

C ontrol LogicR/W Address (9 bits)

Memory Timing: Approaches

Digital Integrated Circuits2nd

Read-Only Memory Cells

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

MOS NOR ROM

Digital Integrated Circuits2nd

MOS NOR ROM Layout

Programmming using the

Digital Integrated Circuits2nd

MOS NOR ROM Layout

Digital Integrated Circuits2nd

MOS NAND ROM

All word lines high by default with exception of selected row

MOS NAND ROM Layout

Digital Integrated Circuits2nd

NAND ROM Layout

Equivalent Transient Model for MOS NOR ROM

Model for NOR ROM

Word line parasitics

Bit line parasitics

Digital Integrated Circuits2nd

Equivalent Transient Model for MOS NAND ROM

Model for NAND ROM

Word line parasitics

Bit line parasitics

Digital Integrated Circuits2nd

Decreasing Word Line Delay

Polysilicon word line

Metal word line

(a) Driving the word line from both sides

Polysilicon word line

(b) Using a metal bypass

Precharged MOS NOR ROM

PMOS precharge device can be made as large as necessary,

Digital Integrated Circuits2nd

Floating-Gate Transistor Programming

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Absolute threshold control

Thin tunneling oxide

Many other options

Cross-sections of NVM cells

Basic Operations in a NOR Flash Memory