Appendix

Attributes
<Signal_name> : IN Std_logic_VECTOR(7 DOWNTO 0)

High - 7
low - 0
Right - 0
Left - 7
Range - 7 downto 0
Reverse range - 0 to 7
Length - 8

Subprograms
Functions
Procedures

Subprograms
Architecture
Begin

Parameters

Function

Return value

Parameters
Out parameters

End

Procedure

Functions
Format:
Function <function_name> (<input_parameters>)
Return <DATA_TYPE> is
{Any declarations}
Begin
{Functionality}
Return <name_of_a_declaration>
End <function_name>;

Functions
For functions:
Only allowable mode for parameters is
in
Only allowed object classes are
constant or signal
If the object class is not specified,
constant is assumed

Procedures
Format:
Procedure <procedure_name> (<mode_parameters>)
Begin
{Functionality}
End <procedure_name>;

Procedures
For procedures:
Allowable modes for parameters are in, out, and inout
Allowable object classes for parameters are constant,
variable and signal
If the mode is in and no object class is specified, then
constant is assumed
If the mode is inout or out and if no object class is
specified, then variable is assumed

Signal Assignment Inside a Process - Delay

Library IEEE;
Use IEEE.Std_logic_1164.ALL;
ENTITY simp_prc IS
Port(a, b : IN Std_logic;
Y: out Std_logic);
END simp_prc;
ARCHITECTURE logic OF simp_prc IS
SIGNAL c: Std_logic;

A = 1, b = 1

C and y
Executed

C updated (c=0)

Y updated (y=x)

Y updated (y=1)

A,b changes
A = 0, b = 1

A,b changes
A = 0, b = 1
C and y
Executed

C and y
Executed
1

Begin
Process(a, b)
Begin
C <= a and b;
Y <= c;
End process;
END logic;

Simulation cycle1
(Visible delay)

Simulation cycle2
(Visible delay)

Y does not get the newest value of c until a

simulation cycle later

C updated (c=1)

Delta cycle has 2 phases:

Process execution
Signal update

Delta cycle is non-visible delay

(Very small, close to zero)

2 Processes

vs.

1 Process

Process1: process(a, b)
Begin

Process(a, b)
Begin
C <= a and b;
Y <= c;
End process;

C <= a and b;
END PROCESS process1;
Process2: process(c)
Begin
Y <= c;
END PROCESS process2;

Y updated
(Y=0)

Y updated
(Y=1)
A=1
B=1

C updated (c=1)

A,b changes
A,b changes
C
C
Updated
Updated
a
=
0
a=1
(C=0)
(C=1)
B=1
B=1

Y
C
Executed Executed
1

Y
Executed

C
Executed
2

Simulation cycle1
(Visible delay)

C
Executed
2

Simulation cycle2
(Visible delay)

C and y gets executed and updated within the

same simulation cycle
10

A = 1, b = 1

C and y
Executed

C updated (c=0)

Y updated (y=x)

Y updated (y=1)

A,b changes
A = 0, b = 1

A,b changes
A = 0, b = 1
C and y
Executed

C and y
Executed
1

Simulation cycle1
(Visible delay)

Simulation cycle2
(Visible delay)

Y does not get the newest value of c until a

simulation cycle later

Variable Assignment - No Delay

Delta Cycle has 2 Phases:

Process Execution
Signal Update

A = 1, b = 1

C
Executed
And
Updated
(C=1)

Library IEEE;
Use IEEE.Std_logic_1164.ALL;
ENTITY var IS
PORT
(a, b : IN Std_logic;
Y : out Std_logic);
END var;
ARCHITECTURE logic OF var IS
Begin
PROCESS (a, b)
VARIABLE c : Std_logic;
BEGIN
C := a AND b;
Y <= c;
END PROCESS;
END logic;

Y updated
(Y=0)

A,b changes
A = 0, b = 1

A,b changes
A = 1, b = 1

C executed and
updated (c=0)

Y
Executed

C executed and
updated (c=1)
Y
Executed

Y
Executed
1

Simulation cycle1
(Visible delay)

Simulation cycle2
(Visible delay)

C and y gets executed and updated within the

same simulation cycle (at the end of the process)

11

Y updated
(Y=1)

Delta cycle is non-visible delay

(Very small, close to zero)

2 Processes

vs.

1 Process

Process1: process(a, b)
Begin

Process(a, b)
Begin
C <= a and b;
Y <= c;
End process;

C <= a and b;
END PROCESS process1;
Process2: process(c)
Begin
Y <= c;
END PROCESS process2;

Y updated
(Y=0)

Y updated
(Y=1)
a=1
b=1

c
updated
(c=1)

A,b changes
a=0
B=1

y
c
executed executed
1

A,b changes
C
Updated
a=1
(C=0)
B=1

A = 1, b = 1

Y
Executed

C and y
Executed

C
Executed
2

Simulation cycle1
(Visible delay)

C updated (c=1)

C
Executed
2

Simulation cycle2
(Visible delay)

C and y gets executed and updated within the

same simulation cycle
12

C updated (c=0)

Y updated (y=x)

Y updated (y=1)

A,b changes
A = 0, b = 1

A,b changes
A = 0, b = 1
C and y
Executed

C and y
Executed
1

simulation cycle1
(visible delay)

simulation cycle2
(visible delay)

Y does not get the newest value of c until a

simulation cycle later